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| 1 the idt logo is a registered trademark of integrated device technology, inc. industrial temperature range ? 2003 integrated device technology, inc. february 16, 2004 dsc-6042/3 features ? programmable dc feeding characteristics ? programmable digital filters adap ting to different requirements: ? impedance matching ? transhybrid balance ? transmit and receive gain adjustment ? frequency response correction ? off-hook and ground-key detection ? ac/dc ring trip detection ? programmable internal balan ced ringing without external components ? supports external ringing ? selectable mpi and gci interfaces ? supports a/-law compressed and linear data formats ? programmable io pins with relay-driving or analog input capability ? line polarity reversal ? integrated fsk generator for sending caller id information ? on-hook transmission ? 2 programmable tone generators per channel ? integrated universal tone det ection (utd) unit for fax/modem tone detection ? integrated test and diagnosis functions (itdf) ? three-party conference ? only battery and 3.3 v power supply needed ? package available: idt82v1671: 28 pin plcc idt82v1074: 100 pin tqfp description the rslic-codec chipset is comprised of one four-channel programmable pcm codec (idt 82v1074) and four single-channel ringing slics (idt82v1671). the chipset provides a total solution for line card designs. in addition to providing a complete software programmable solution for borscht, additional functions such as fsk generator, universal tone detection (utd) unit, tone generators, ringing generator, integrated test and diagnosis functions (itdf), line polarity reversal and three-party conference are integrated in to the chipset. the high integration of system functi ons reduces board space requirements of the line card and saves cost. the chipset is fully programmabl e via a microprocessor interface (mpi) or a general circuit interfac e (gci). in both mpi and gci modes, the chipset supports a/-law companding format or linear data format. programmable digital filters on the chipset provide the necessary transmit and receive filtering to r ealize impedance matching, transhybrid balance, frequency response corr ection and transmit/receive gains adjustment. the full programmability optimizes the performance of line card products and allows one line card to adapt to different requirements worldwide. the powerful integrated test and diagnosis functions (itdf) accomplish necessary tests and m easurements without external test equipment or relays. this brings convenience to system maintenance and diagnosis. this chipset can be used in digital telecommunication applications such as voip, voatm, pbx, co and dlc etc. chipset functional block diagram rslic 1 # rslic 2 # rslic 3 # rslic 4 # level metering off-hook detection dc feed dsp filtering mpi interface pcm/gci interface cid utd self test codec pcm/gci telephone telephone telephone telephone protection circuit protection circuit protection circuit protection circuit microprocessor chipset of ringing subscriber line interface circuit (rslic) & quad programmable pcm codec idt82v1671 (rslic) idt82v1074 (codec)
2 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range rslic functional block diagram battery switch line driver ring trip il sense it sense input stage logic control vbl vbh vcm vdd gnd vl vtdc vtac ca acn acp dcn dcp cs m1 m2 m3 rt rsn rsp tip ring tis ris 3 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range codec functional block diagram filter and a/d for ac d/a and filter for ac general control logic filter and a/d for dc d/a and filter for dc slic signaling channel1 for ac channel1 for dc dsp core channel2 for ac channel3 for ac channel4 for ac channel2 for dc channel3 for dc channel4 for dc pll and clock generation mpi interface pcm/gci interface mpi /gci reset dr1/dd dr2 dx1/du dx2 fsc bclk/dcl tsx1 tsx2 cclk/s0 ci/s1 co cs mclk 4 i/os cs1 acp1 acn1 vtac1 vtdc1 dcp1 dcn1 slic interface control m1 m2 m3 int /int 4 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range table of contents 1 pin configurations ............................................................................................................ .................................................................................9 1.1 rslic pin configuration ..................................................................................................... ......................................................................9 1.2 codec pin configuration ..................................................................................................... ..................................................................10 2 pin descriptions.............................................................................................................. .................................................................................11 2.1 rslic pin description....................................................................................................... ......................................................................11 2.2 codec pin description ....................................................................................................... ...................................................................12 3 functional description ........................................................................................................ ............................................................................16 3.1 functions overview .......................................................................................................... .......................................................................16 3.1.1 basic functions ........................................................................................................... ...............................................................16 3.1.2 additional functions ...................................................................................................... .............................................................16 3.1.3 programmable functions .................................................................................................... .......................................................16 3.2 dc feeding .................................................................................................................. ...........................................................................17 3.2.1 dc feeding characteristic zones ........................................................................................... ...................................................17 3.2.2 constant current zone..................................................................................................... ..........................................................17 3.2.3 resistive zone............................................................................................................ ................................................................17 3.2.4 constant voltage zone..................................................................................................... ..........................................................17 3.2.5 dc feeding characteristics configuration .................................................................................. ...............................................18 3.3 speech processing........................................................................................................... .......................................................................20 3.3.1 ac transmission ........................................................................................................... .............................................................20 3.3.1.1 transmit path .......................................................................................................... ..................................................20 3.3.1.2 receive path ............................................................................................................ ..................................................21 3.3.2 programmable filters ...................................................................................................... ...........................................................21 3.3.2.1 impedance matching ...................................................................................................... ............................................21 3.3.2.2 transhybrid balance..................................................................................................... ..............................................22 3.3.2.3 frequency response correction........................................................................................... .....................................22 3.3.2.4 gain adjustment ......................................................................................................... ................................................22 3.4 ring and ring trip.......................................................................................................... .........................................................................23 3.4.1 internal ringing mode ..................................................................................................... ...........................................................23 3.4.1.1 internal ringing generation............................................................................................. ...........................................23 3.4.1.2 ring trip detection in internal ringing mode............................................................................ .................................23 3.4.2 external ringing mode ..................................................................................................... ..........................................................24 3.4.2.1 ring trip detection in external ringing mode............................................................................ ................................25 3.5 supervision................................................................................................................. .............................................................................27 3.5.1 off-hook detection ........................................................................................................ .............................................................27 3.5.2 ground-key detection...................................................................................................... ..........................................................29 3.6 metering by polarity reversal............................................................................................... ...................................................................29 3.7 enhanced signal processing.................................................................................................. .................................................................30 3.7.1 tone generator ............................................................................................................ ..............................................................30 3.7.1.1 dtmf generation......................................................................................................... ..............................................30 3.7.2 fsk generation for caller id .............................................................................................. .......................................................30 3.7.3 universal tone detection (utd) ............................................................................................ ....................................................34 3.7.3.1 introduction............................................................................................................ .....................................................34 3.7.3.2 utd principle ........................................................................................................... ..................................................34 3.7.3.3 utd programming......................................................................................................... .............................................36 3.8 three-party conference ...................................................................................................... ....................................................................37 3.8.1 introduction.............................................................................................................. ...................................................................37 3.8.2 pcm interface configuration ............................................................................................... .......................................................37 3.8.3 control the active pcm channels........................................................................................... ...................................................38 3.9 itdf........................................................................................................................ .................................................................................40 3.9.1 introduction.............................................................................................................. ...................................................................40 3.9.2 diagnosis and test functions .............................................................................................. ......................................................40 3.9.3 integrated signal generators .............................................................................................. .......................................................40 3.9.4 level meter............................................................................................................... ..................................................................40 3.9.4.1 level meter source selection............................................................................................ .........................................40 5 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.9.4.2 level meter gain filter and rectifier ................................................................................... .......................................41 3.9.4.3 level meter integrator .................................................................................................. ..............................................42 3.9.4.4 level meter result register ............................................................................................. ..........................................43 3.9.4.5 level meter shift factor ................................................................................................ .............................................43 3.9.4.6 level meter threshold setting........................................................................................... .........................................43 3.9.5 measurement via ac level meter ............................................................................................ ..................................................45 3.9.5.1 current measurement via vtac............................................................................................ .....................................45 3.9.5.2 ac level meter operational state flow ................................................................................... ..................................45 3.9.6 measurement via dc level meter............................................................................................ ..................................................45 3.9.6.1 offset current measurement .............................................................................................. ........................................45 3.9.6.2 leakage current measurement............................................................................................. .....................................45 3.9.6.3 loop resistance measurement............................................................................................. .....................................46 3.9.6.4 line resistance tip/gnd and ring/gnd.................................................................................... ...............................46 3.9.6.5 capacitance measurement................................................................................................. ........................................47 3.9.6.6 voltage measurement ..................................................................................................... ...........................................48 3.9.6.7 voltage offset measurement.............................................................................................. ........................................49 3.9.6.8 ring trip operational am plifier offset measurement...................................................................... ...........................49 4 interface ..................................................................................................................... .......................................................................................50 4.1 pcm/mpi interface ........................................................................................................... .......................................................................50 4.1.1 mpi control interface ..................................................................................................... ............................................................50 4.1.2 pcm interface ............................................................................................................. ...............................................................51 4.1.2.1 pcm clock configuration ................................................................................................. ..........................................51 4.1.2.2 time slot assignment.................................................................................................... .............................................52 4.1.2.3 pcm highway selection ................................................................................................... ..........................................52 4.2 gci interface ............................................................................................................... ............................................................................52 4.2.1 compressed gci mode....................................................................................................... .......................................................52 4.2.2 linear gci mode ........................................................................................................... .............................................................52 4.2.3 command/indication (c/i) channel .......................................................................................... ..................................................55 4.2.3.1 downstream c/i channel byte ............................................................................................. ......................................55 4.2.3.2 upstream c/i channel byte............................................................................................... .........................................55 4.2.4 gci monitor transfer protocol............................................................................................. .......................................................56 4.2.4.1 monitor channel operation ............................................................................................... .........................................56 4.2.4.2 monitor handshake procedure............................................................................................. ......................................56 4.3 analog pots interface....................................................................................................... .....................................................................58 4.4 rslic and codec interface ................................................................................................... ...............................................................58 5 programming................................................................................................................... .................................................................................59 5.1 overview.................................................................................................................... ..............................................................................59 5.1.1 mpi programming ........................................................................................................... ...........................................................59 5.1.1.1 broadcast mode for mpi programming ...................................................................................... ................................59 5.1.1.2 identification code for mpi programming................................................................................. ..................................59 5.1.2 gci programming ........................................................................................................... ...........................................................59 5.1.2.1 program start byte for gci programming.................................................................................. ................................59 5.1.2.2 identification command for gci programming.............................................................................. .............................59 5.2 register/ram commands....................................................................................................... ................................................................59 5.2.1 register/ram command format ............................................................................................... ................................................59 5.2.2 addressing the local registers............................................................................................ ......................................................59 5.2.3 addressing the global registers........................................................................................... .....................................................60 5.2.4 addressing the fsk-ram .................................................................................................... ......................................................60 5.2.5 addressing the coe-ram.................................................................................................... .......................................................61 5.3 registers description ....................................................................................................... .......................................................................63 5.3.1 registers overview ........................................................................................................ ............................................................63 5.3.2 global registers list ..................................................................................................... .............................................................65 5.3.3 local registers list ...................................................................................................... ..............................................................73 5.4 programming examples ........................................................................................................ ..................................................................83 5.4.1 programming examples for mpi mode......................................................................................... ..............................................83 5.4.1.1 example of programming the local registers via mpi ...................................................................... ........................83 6 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 5.4.1.2 example of programming the global registers via mpi..................................................................... ........................84 5.4.1.3 example of programming the coefficient-ram via mpi...................................................................... .......................84 5.4.1.4 example of programming the fsk-ram via mpi.............................................................................. .........................84 5.4.2 programming examples for gci mode......................................................................................... ..............................................85 5.4.2.1 example of programming the local registers via gci ...................................................................... ........................85 5.4.2.2 example of programming the global registers via gci..................................................................... ........................85 5.4.2.3 example of programming the coefficient-ram via gci...................................................................... .......................85 5.4.2.4 example of programming the fsk-ram via gci.............................................................................. .........................86 6 operational description ....................................................................................................... ...........................................................................87 6.1 operating modes ............................................................................................................. ........................................................................87 6.1.1 rslic control signaling ................................................................................................... .........................................................87 6.1.2 rslic operating modes ..................................................................................................... .......................................................89 6.1.3 codec operating modes..................................................................................................... .....................................................89 6.2 pll power down.............................................................................................................. .......................................................................90 6.3 programmable i/os of the codec .............................................................................................. ...........................................................90 6.4 interrupt handling .......................................................................................................... ..........................................................................91 6.5 signal path and test loopbacks.............................................................................................. ...............................................................91 6.6 rslic power on sequence..................................................................................................... ...............................................................93 6.7 codec power on sequence ..................................................................................................... ............................................................93 6.8 default state after reset................................................................................................... ......................................................................93 6.8.1 power-on reset and hardware reset......................................................................................... ..............................................93 6.8.2 software reset............................................................................................................ ...............................................................93 7 electrical characteristics .................................................................................................... ............................................................................94 7.1 rslic electrical characteristics............................................................................................ ..................................................................94 7.1.1 rslic absolute maximum ratings ............................................................................................ ................................................94 7.1.2 rslic recommended operating conditions.................................................................................... .........................................94 7.1.3 rslic thermal information................................................................................................. .......................................................94 7.1.4 rslic power consumption ................................................................................................... ....................................................94 7.2 codec electrical characteristics ............................................................................................ ...............................................................95 7.2.1 codec absolute maximum ratings............................................................................................ ..............................................95 7.2.2 codec recommended operating conditions .................................................................................... ......................................95 7.2.3 codec digital interface ................................................................................................... .........................................................95 7.2.4 codec power dissipation................................................................................................... ......................................................95 7.3 chipset transmission characteristics ........................................................................................ .............................................................96 7.3.1 absolute gain............................................................................................................. ................................................................96 7.3.2 gain tracking ............................................................................................................. ................................................................96 7.3.3 frequency response ........................................................................................................ .........................................................96 7.3.4 return loss ............................................................................................................... .................................................................96 7.3.5 group delay ............................................................................................................... ................................................................97 7.3.6 distortion ................................................................................................................ ....................................................................97 7.3.7 noise ..................................................................................................................... .....................................................................97 7.3.8 interchannel crosstalk.................................................................................................... ............................................................98 7.4 codec timing characteristics ................................................................................................ ...............................................................99 7.4.1 clock timing.............................................................................................................. .................................................................99 7.4.2 microprocessor interface timing ........................................................................................... ...................................................100 7.4.3 pcm interface timing...................................................................................................... .........................................................101 7.4.4 gci interface timing ...................................................................................................... ..........................................................103 8 application circuits .......................................................................................................... .............................................................................104 8.1 application circuit for the internal ringing mode ........................................................................... .......................................................104 8.2 application circuit for the external ringing mode ........................................................................... ......................................................105 9 ordering information .......................................................................................................... ...........................................................................106 7 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range list of figures figure - 1 line circuit functions included in the rslic-codec chipset ........................................................... ............................................. 16 figure - 2 dc feeding zones ..................................................................................................... ....................................................................... 17 figure - 3 constant current zone................................................................................................ ...................................................................... 17 figure - 4 resistive zone....................................................................................................... ............................................................................ 17 figure - 5 constant voltage zone................................................................................................ ...................................................................... 18 figure - 6 dc feeding characte ristics configuration ............................................................................. ........................................................... 18 figure - 7 dc feeding configuration ex ample for short loop applications......................................................... ............................................. 18 figure - 8 signal paths for ac transmission..................................................................................... ................................................................ 20 figure - 9 voice signal path of the codec ....................................................................................... ............................................................... 20 figure - 10 nyquist diagram..................................................................................................... ........................................................................... 21 figure - 11 internal balanced ringing ........................................................................................... ...................................................................... 23 figure - 12 external ringing synchronization .................................................................................... ................................................................. 25 figure - 13 hysteresis for off-hook detection................................................................................... .................................................................. 27 figure - 14 debounce filter for off-hook/ground-key detection ................................................................... ...................................................... 28 figure - 15 fsk signal transmission sequence.................................................................................... ............................................................. 31 figure - 16 recommended programming fl ow chart for fsk generation ............................................................... .......................................... 33 figure - 17 utd functional diagram.............................................................................................. ..................................................................... 34 figure - 18 example of utd recognition timing ................................................................................... ............................................................. 35 figure - 19 example of utd tone end detection timing ............................................................................ ....................................................... 35 figure - 20 conference block diagram ............................................................................................ ................................................................... 37 figure - 21 level meter block diagram ........................................................................................... .................................................................... 41 figure - 22 continuous measurement sequence (ac & dc level meter) ............................................................... ........................................... 42 figure - 23 single measurement sequence (ac & dc level meter) ................................................................... ............................................... 42 figure - 24 example for resistance measurement .................................................................................. ........................................................... 46 figure - 25 differential resistance measurement ................................................................................. .............................................................. 46 figure - 26 capacitance measurement ............................................................................................. .................................................................. 47 figure - 27 external voltage measurement principle .............................................................................. ............................................................ 48 figure - 28 mpi read operation timing........................................................................................... ................................................................... 50 figure - 29 mpi write operation timing .......................................................................................... .................................................................... 50 figure - 30 pcm clock slope select waveform..................................................................................... ............................................................. 51 figure - 31 compressed gci frame structure...................................................................................... .............................................................. 53 figure - 32 linear gci frame structure .......................................................................................... .................................................................... 54 figure - 33 monitor channel operation ........................................................................................... .................................................................... 56 figure - 34 state diagram of the monitor transmitter ............................................................................ ............................................................. 57 figure - 35 state diagram of the monitor receiver ............................................................................... .............................................................. 58 figure - 36 waveform of programming exam ple: writing to local registers ......................................................... ............................................ 83 figure - 37 waveform of programming example: reading local registers ............................................................ ........................................... 83 figure - 38 rslic mode control signaling ........................................................................................ ................................................................. 87 figure - 39 rslic control timing diagram........................................................................................ ................................................................. 88 figure - 40 rslic internal test circuit......................................................................................... ....................................................................... 89 figure - 41 io debounce filter .................................................................................................. .......................................................................... 90 figure - 42 ac/dc signal path and test loopbacks ................................................................................ .......................................................... 92 figure - 43 clock timing........................................................................................................ .............................................................................. 99 figure - 44 mpi input timing .................................................................................................... ......................................................................... 100 figure - 45 mpi output timing ................................................................................................... ....................................................................... 100 figure - 46 pcm interface ti ming (single clock mode) ............................................................................ ........................................................ 101 figure - 47 pcm interface ti ming (double clock mode)............................................................................ ....................................................... 102 figure - 48 gci interface timing ................................................................................................ ....................................................................... 103 figure - 49 application circuit for the internal ringing mode ................................................................... ......................................................... 104 figure - 50 application circuit for the external ringing mode ................................................................... ........................................................ 105 8 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range list of tables table - 1 registers and coe-ram locations used for dc feeding configuration..................................................... ......................................19 table - 2 registers and coe-ram locations used for internal ringing mode ........................................................ .........................................24 table - 3 registers and coe-ram locations used for external ringing mode ........................................................ ........................................26 table - 4 off-hook detection in different modes ................................................................................. ..............................................................27 table - 5 registers and coe-ram locations used for off-hook detection ........................................................... ...........................................28 table - 6 registers used for ground-key detection............................................................................... ...........................................................29 table - 7 registers and coe-ram locations used for tone generation .............................................................. ...........................................30 table - 8 fsk modulation characteristics ........................................................................................ .................................................................31 table - 9 registers and fsk-ram used for the fsk generator ...................................................................... ................................................32 table - 10 registers and coe-ram locations used for utd ......................................................................... ....................................................36 table - 11 conference mode...................................................................................................... .........................................................................38 table - 12 active pcm channel configuration bits................................................................................ .............................................................38 table - 13 level meter source selection ......................................................................................... ...................................................................40 table - 14 level meter result value range....................................................................................... .................................................................43 table - 15 shift factor selection ............................................................................................... ..........................................................................43 table - 16 level meter threshold setting ........................................................................................ ...................................................................43 table - 17 registers and coe-ram locat ions used for the level meter............................................................. ...............................................44 table - 18 registers and coe-ram locations used for ramp generator.............................................................. ............................................48 table - 19 time slot select ion for compressed gci ............................................................................... ..........................................................53 table - 20 time slot sele ction for linear gci................................................................................... .................................................................54 table - 21 local register addressing in mpi mode ................................................................................ ............................................................60 table - 22 local register addressing in gci mode ................................................................................ ............................................................60 table - 23 coefficient ram mapping.............................................................................................. .....................................................................62 table - 24 global registers mapping ............................................................................................. .....................................................................63 table - 25 local registers mapping.............................................................................................. ......................................................................64 table - 26 rslic operating mode ................................................................................................. .....................................................................89 table - 27 interrupt source and interrupt mask.................................................................................. .................................................................91 table - 28 external components in application circuits .......................................................................... .........................................................105 9 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 1 pin configurations 1.1 rslic pin configuration idt82v1671 idt82v1671 vbh vbl tip ring 1 28 27 26 2 3 4 ris bgnd tis 19 20 21 22 23 24 25 18 17 16 15 14 13 12 5 6 7 8 9 10 11 m2 m1 cs rt rsn rsp vcmb m3 cb vl vtdc ca vtac dcp vdd agnd cf vcm acn acp dcn 10 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 1.2 codec pin configuration vdda4 io1_3 io4_3 io3_3 io2_3 iognd io4_4 io3_4 io2_4 io1_4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 acn1 vtdc1 dcn1 vl1 vtac1 agnd dcp1 ca1_1 ca2_1 acp1 io4_2 io3_2 io2_2 io1_2 iognd io4_1 io3_1 io2_1 io1_1 rtin1 acn4 acp3 agnd acn3 agnd ca1_3 ca2_3 dcn3 dcp3 vtac3 vtdc3 vl3 rtin3 vdda3 cnf agnd vtac2 vtdc2 vl2 vdda2 vcm ca1_2 dcp2 rtin2 vddb dr2 dx1/du fsc vddd tsx2 dx2 dr1/dd tsx1 reset mclk dgnd dgnd rsync mpi /gci ci/s1 m2 m3 test m1 cclk/s0 cs2 cs1 c0 vddd cs agnd dcp4 ca1_4 vl4 vtdc4 vtac4 rtin4 acp4 ca2_4 dcn4 idt82v1074 vdda1 dcn2 acp2 acn2 ca2_2 cs3 dcl/bclk int /int vddio cs4 11 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range 2 pin descriptions 2.1 rslic pin description name type pin number description vbh power 1 negative battery supply ( ? 70 v vbh ? 52 v) ris ? 2 ring sense, connected to the ring pin through an external resistor r s . refer to ?8 application circuits? on page 104 for details. bgnd power 3 battery ground. this pin should be externally connected to agnd. tis ? 4 tip sense, connected to the tip pin through an external resistor r s . vdd power 5 +3.3 v power supply. agnd power 6 analog ground. this pin should be externally connected to bgnd. cf 7 output voltage of vbat/2 (vbat represents the selected battery voltage vbh or vbl). an external capacitor is connected between this pin and the ground for filtering. vcm i 8 reference voltage input, typical 1.5 v. acn i 9 differential ac voltage, negative. acp i 10 differential ac voltage, positive. dcn i 11 differential dc voltage, negative. dcp i 12 differential dc voltage, positive. vtac o 13 sense transversal ac voltage. ca ? 14 external capacitor connection. an external capacitor is connected between this pin and the cb pin to separate the dc component from the sense transversal voltage. vtdc o 15 sense transversal dc voltage. vl o 16 sense longitudinal voltage. cb ? 17 external capacitor connection. an external capacitor is connected between this pin and the ca pin to separate the dc component from the sense transversal voltage. m3 i/o 18 mode control input 3 or temperature information output. the logic level of the cs pin determines the direction of the m3 pin. see the description of the cs pin for details. m2 i 19 mode control input 2. this is a binary logic pin, together with m1 and m3, controlling the operating mode of the rslic. m1 i 20 mode control input 1. this is a binary logic pin, together with m2 and m3, controlling the operating mode of the rslic. cs i21 chip select input. it is a ternary logic pin. when the cs pin is logic 0 (0 v< cs < 0.8 v) , the rslic receives the mode control data from the codec through the m1 to m3 pins. when the cs pin is logic 1 (2.2 v< cs < 3.3 v) , the rslic sends the temperature information of itself to the codec through the m3 pin. when the cs pin is 1.5 v (with 0.5 v tolerance ), the rslic neither receives the data from the codec nor sends temperature information to it. rt o 22 ring trip operational amplifier output. rsn i 23 negative ring trip operational amplifier input. rsp i 24 positive ring trip operational amplifier input. vcmb o 25 vcm buffer output, 1.5 v, used for external ringing mode. ring i/o 26 subscriber loop connection ring. tip i/o 27 subscriber loop connection tip. vbl power 28 negative battery supply ( ? 52 v vbl ? 20 v). 12 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range 2.2 codec pin description name type pin number description vtdc1 i 33 dc component of the transversal voltage (channel 1). vtac1 i 34 ac component of transversal voltage (channel 1). vl1 i 32 longitudinal voltage (channel 1). rtin1 i 31 analog voltage that can be used for external ring trip detection (channel 1). acp1 o 40 differential ac voltage, positive (channel 1). acn1 o 41 differential ac voltage, negative (channel 1). dcp1 o 36 differential dc voltage, positive (channel 1). dcn1 o 39 differential dc voltage, negative (channel 1). cs1 o 52 ternary logic output 1, controlling the operating mode of the rslic1 (channel 1). when the cs1 pin is logic 0 (0 v< cs1 < 0.8 v) , the codec sends mode control data to the rslic1 through the m1 to m3 pins. when the cs1 pin is logic 1 (2.2 v< cs1 < 3.3 v) , the codec receives the temperature information of the rslic1 through the m3 pin. when the cs1 pin is 1.5 v (with 0.5 v tolerance ), no mode control data or temperature information is transferred between the codec and the rslic1. io1_1 i/o 50 programmable io pin with relay-driving capability (channel 1). in external ringing mode, the io1_1 pin can be used to control the external ring relay. io2_1 i/o 49 programmable io pin with relay-driving capability (channel 1). io3_1 i/o 48 programmable io pin with analog input functionality (channel 1). io4_1 i/o 47 programmable io pin with analog input functionality (channel 1). ca1_1 i/o 37 external capacitor connection. an external capacitor is connected between this pin and the dcp1 pin for filtering (ch annel 1). ca2_1 i/o 38 external capacitor connection. an external capacitor is connected between this pin and the dcn1 pin for filtering (ch annel 1). vtdc2 i 21 dc component of the transversal voltage (channel 2). vtac2 i 22 ac component of the transversal voltage (channel 2). vl2 i 20 longitudinal voltage (channel 2). rtin2 i 19 analog voltage that can be used for external ring trip detection (channel 2). acp2 o 28 differential ac voltage, positive (channel 2). acn2 o 29 differential ac voltage, negative (channel 2). dcp2 o 24 differential dc voltage, positive (channel 2). dcn2 o 27 differential dc voltage, negative (channel 2). cs2 o 51 ternary logic output 2, controlling the operating mode of the rslic2 (channel 2). when the cs2 pin is logic 0 (0 v< cs2 < 0.8 v) , the codec sends mode control data to the rslic2 through the m1 to m3 pins. when the cs2 pin is logic 1 (2.2 v< cs2 < 3.3 v) , the codec receives the temperature information of the rslic2 through the m3 pin. when the cs2 pin is 1.5 v (with 0.5 v tolerance ), no mode control data or temperature information is transferred between the codec and the rslic2. io1_2 i/o 45 programmable io pin with relay-driving capability (channel 2). in external ringing mode, the io1_2 pin can be used to control the external ring relay. io2_2 i/o 44 programmable io pin with relay-driving capability (channel 2). io3_2 i/o 43 programmable io pin with analog input functionality (channel 2). io4_2 i/o 42 programmable io pin with analog input functionality (channel 2). ca1_2 i/o 25 external capacitor connection. an external capacitor is connected between this pin and the dcp2 pin for filtering (ch annel 2). ca2_2 i/o 26 external capacitor connection. an external capacitor is connected between this pin and the dcn2 pin for filtering (ch annel 2). 13 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range vtdc3 i 5 dc component of the transversal voltage (channel 3). vtac3 i 6 ac component of the transversal voltage (channel 3). vl3 i 4 longitudinal voltage (channel 3). rtin3 i 3 analog voltage that can be used for external ring trip (channel 3). acp3 o 12 differential ac voltage, positive (channel 3). acn3 o 13 differential ac voltage, negative (channel 3). dcp3 o 8 differential dc voltage, positive (channel 3). dcn3 o 11 differential dc voltage, negative (channel 3). cs3 o 80 ternary logic output 3, controlling the operating mode of the rslic3 (channel 3). when the cs3 pin is logic 0 (0 v< cs3 < 0.8 v) , the codec sends mode control data to the rslic3 through the m1 to m3 pins. when the cs3 pin is logic 1 (2.2 v< cs3 < 3.3 v) , the codec receives the temperature information of the rslic3 through the m3 pin. when the cs3 pin is 1.5 v (with 0.5 v tolerance ), no mode control data or temperature information is transferred between the codec and the rslic3. io1_3 i/o 86 programmable io pin with relay-driving capability (channel 3). in external ringing mode, the io1_3 pin can be used to control the external ring relay. io2_3 i/o 87 programmable io pin with relay-driving capability (channel 3). io3_3 i/o 88 programmable io pin with analog input functionality (channel 3). io4_3 i/o 89 programmable io pin with analog input functionality (channel 3). ca1_3 i/o 9 external capacitor connection. an external capacitor is connected between this pin and the dcp3 pin for filtering (cha nnel 3). ca2_3 i/o 10 external capacitor connection. an external capacitor is connected between this pin and the dcn3 pin for filtering (ch annel 3). vtdc4 i 93 dc component of the transversal voltage (channel 4). vtac4 i 94 ac component of the transversal voltage (channel 4). vl4 i 92 longitudinal voltage (channel 4). rtin4 i 91 analog voltage that can be used for external ring trip (channel 4). acp4 o 100 differential ac voltage, positive (channel 4). acn4 o 1 differential ac voltage, negative (channel 4). dcp4 o 96 differential dc voltage, positive (channel 4). dcn4 o 99 differential dc voltage, negative (channel 4). cs4 o 79 ternary logic output 4, controlling the operating mode of the rslic4 (channel 4). when the cs4 pin is logic 0 (0 v< cs4 < 0.8 v) , the codec sends mode control data to the rslic4 through the m1 to m3 pins. when the cs4 pin is logic 1 (2.2 v< cs4 < 3.3 v) , the codec receives the temperature information of the rslic4 through the m3 pin. when the cs4 pin is 1.5 v (with 0.5 v tolerance ), no mode control data or temperature information is transferred between the codec and the rslic4. io1_4 i/o 81 programmable io pin with relay-driving capability (channel 4). in external ringing mode, the io1_4 pin can be used to control the external ring relay. io2_4 i/o 82 programmable io pin with relay-driving capability (channel 4). io3_4 i/o 83 programmable io pin with analog input functionality (channel 4). io4_4 i/o 84 programmable io pin with analog input functionality (channel 4). ca1_4 i/o 97 external capacitor connection. an external capacitor is connected between this pin and the dcp4 pin for filtering (ch annel 4). ca2_4 i/o 98 external capacitor connection. an external capacitor is connected between this pin and the dcn4 pin for filtering (ch annel 4). name type pin number description 14 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range m1 o 54 rslic operating mode control output 1. the m1to m3 pins together with the csn pin (n = 1 to 4 for channel 1 to 4 respectively) determine the operating mode of the rslic connected to channel n of the codec. refer to the description of the csn pin for details. m2 o 55 rslic operating mode control output 2. see the description of the m1 pin for details. m3 i/o 56 rslic operating mode control output 3 or rslic temperature information input. the direction of this pin is determined by the logic level of the csn pin (n = 1 to 4 for channel 1 to 4 respectively): csn = 0: m3 is an output pin. it, together with m1 and m2, carries the mode control data to rslicn; csn = 1: m3 is an input pin, carrying the temperature information of rslicn to the codec. mpi /gci i 60 interface mode selection. logic 0 selects mpi mode and logic 1 selects gci mode. fsc i 75 frame synchronization clock for pcm or gci interface. the fsc signal is 8 khz, identifying the beginning of the pcm frame (mpi mode) or indicating the beginning of time slot 0 in gci frame (gci mode). dcl/bclk i 76 pcm bit clock (bclk) for mpi mode or data clock (dcl) for gci mode. in mpi mode, the pcm data is transferred between the code c and the pcm highway, following the bclk. the bclk is required to be synchronous to the fsc. the frequency of t he bclk can be from 256 khz to 8.192 mhz in steps of 64 khz. in gci mode, the dcl is either 2.048 mhz or 4.096 mhz. the internal circuit of the codec automatically monitors this input to determine which frequency is being used. dx1/du o 69 data transmit pcm highway one (for mpi mode) or data upstream (for gci mode). in mpi mode, the pcm data is transmitted to the pcm highway one (dx1) or two (dx2), following the bclk. in gci mode, the gci data of all four channels is transmitted via the du pin to the master device. dr1/dd i 70 data receive pcm highway one (for mpi mode) or data downstream (for gci mode). in mpi mode, the pcm data is received from pcm highway one (dr1) or two (dr2), following the bclk. in gci mode, the gci data is received from the master device via the dd pin. tsx1 o 68 transmit indicator for pcm highway one, open drain. this pin becomes low when the data is transmitted via dx1. tsx2 o 72 transmit indicator for pcm highway two, open drain. this pin becomes low when the data is transmitted via dx2. dx2 o 73 data transmit pcm highway two (for mpi mode). refer to the description of the dx1 pin for details. dr2 i 74 data receive pcm highway two (for mpi mode). refer to the description of the dr1 pin for details. cclk/s0 i 62 control clock (cclk) for mpi mode or time slot selection 0 (s0) for gci mode. in mpi mode, the cclk pin provides clock for the serial control interface. the frequency of the cclk can be up to 8.192 mhz. in gci mode, the s0 together with time slot selection 1 (s1) determines which time slot is used to transmit the voice or contro l data. co o 64 control data output (co) for mpi mode. ci/s1 i 63 control data input (ci) for mpi mode or time slot selection 1 (s1) for gci mode.refer to the description of the s0 pin for details. cs i 61 codec chip selection signal for mpi mode, active low. mclk i 66 master clock input. the mclk pin provides the clock for the dsp of the codec. the frequency of the mclk can be 1.536 mhz, 1.544 mhz, 2.048 mhz, 3.072 mhz, 3.088 mhz, 4.096 mhz, 6.144 mhz, 6.176 mhz or 8.192 mhz. int /int o 77 interrupt output pin for mpi mode. the active level of this pin is programmable. if any of the active interrupts occurs, this p in will be set to active level, high or low. it is active low by default. vcm o 17 reference voltage output. typical 1.5 v. reset i 67 reset signal input. active low. rsync i 59 external ringing synchronization signal. in external ringing mode, the synchronization signal provided by the external ringer i s applied to the codec via this pin. the external relay can be switched on or off by the io1 pin synchronously following the rsync. test i 57 input pin for internal test purpose. this pin must be connected to the ground. cnf ? 15 external capacitor connection. an external capacitor is connected between this pin and the agnd for noise filtering. vdda1 vdda2 vdda3 vdda4 power 30 18 2 90 +3.3 v analog power supply. vddd power 71, 53 +3.3 v digital power supply. vddb power 16 +3.3 v bias power supply. name type pin number description 15 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range vddio power 78 power supply for io pins. agnd power 7, 14, 23, 35, 95 analog ground. dgnd power 58, 65 digital ground. iognd power 46, 85 ground for io pins. name type pin number description 16 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3 functional description 3.1 functions overview 3.1.1 basic functions all borscht functions are integrated in the rslic-codec chipset: ? battery feeding the chipset provides programmabl e dc feeding characteristics. ? over voltage protection over voltage protection is r ealized by the rslic and additional protection circuits. ? ringing the chipset supports both inter nal and external ringing modes. ? supervision (signaling) the chipset supports off-hook and ground-key detection, dc and ac ring trip detection. ? coding supports a/-law compressed code and linear code. ?hybrid provides hybrid for 2/4-wire conversion. ? testing supports integrated test and diagnostic functions (itdf). 3.1.2 additional functions besides full borscht functions, the following additional functions are also integrated in the rslic-codec chipset: ? tone generators the codec provides two tone generators (tg1 & tg2) per channel. the tone generators can be used to generate dtmf signals, test tones, dial tones etc. ? fsk generator the chipset provides a built-i n fsk generator for sending caller id information. ? universal tone detection (utd) the chipset provides a built-i n utd unit per channel to detect special tones in the receive or transmit path (fax and modem tones, for example) ? line polarity reversal the chipset supports teletax metering by reversing the polarity of the tip/ring voltage. 3.1.3 programmable functions the rslic-codec chipset provides a highly flexible programmable solution for line card designs. by programming the corresponding registers or coefficient ram in the codec, users can design one line card to meet different requirement s worldwide. that means, adjusting the receive/transmit gain and the tr anshybrid balance can be realized by software with a single hardware design. the chipset provides many pr ogrammable functions including: ? dc feeding characteristics ? impedance matching ? transhybrid balance ? frequency response correction in transmit and receive paths ? gain in transmit and receive paths ? off-hook and ground-key detect threshold and debounce interval ? ac and dc ring trip thresholds ? internal ringing frequency, amp litude and dc ringing offset voltage ? analog and digital test loopbacks these functions are described in detail in the following chapters. figure - 1 line circuit functions included in the rslic-codec chipset battery switch line driver filter adc dac programmable filters and gain pcm compander timeslot assignment off-hook detector ground key detector ring generator ring trip detector polarity reverse itdf utd fsk generator tone generators ramp generator pcm/gci interface serial control interface slic control interface general control logic dsp core channel 1 channel 2 rslic 2 # codec rslic 1 # rslic 3 # rslic 4 # mpi interface pcm interface gci interface ring tip ring tip ring tip ring tip input stage logic control ring trip current sensor channel 3 channel 4 channel 2 17 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.2 dc feeding 3.2.1 dc feeding characteristic zones analog telephones require a dc current in the off-hook state with ac voice signals in the transmit and receiv e directions superimposed. thus, once the telephone has gone off-hook, the slic must supply a dc current to the subscriber line. t he rslic-codec chipset provides a fully programmable dc feeding characte ristic to meet the requirements of different applications. the dc feeding characteristic has three different zones: the constant current zone, the resistive zone and the constant voltage zone (see figure - 2 ). a voltage reserve v res is provided to avoid clipping the high level ac signal. 3.2.2 constant current zone in applications of short local l oops, the dc feeding can be considered as an ideal current source with an infinite internal resistance ( r i ), see figure - 3. when the loop is in the off-hook state, the feeding current usually must be kept at a constant level independent of the load. the rslic senses the dc current and prov ides this information to codec via the vtdc pin. the codec compares this value with the programmed value and adjusts t he rslic drivers as required. depending on the load, the operating point is determined by the voltage v tip/ring between the tip and ring lines as follows: v tip/ring = r l ? i tip/ring where, r l represents the equivalent loop resistance. the lower the load resistance r l , the lower the voltage v tip/ring . when the dc feeding is operating in the constant current zone, the indication bit feed_i in register lr eg21 will be set to 1, otherwise it is set to 0. 3.2.3 resistive zone the resistive zone is flexible in a wide range of applications, especially applicable to medium line loops where the battery is unable to feed a constant current to the line. in this zone, the dc feeding is considered as a voltage source with a programmable internal resistance (r lin ) . the operating point crosses from t he constant current zone to the resistive zone, as shown in figure - 4 . when the dc feeding is operating in the resistive zone, the indication bit feed_r in register lreg21 will be set to 1, ot herwise it is set to 0. 3.2.4 constant voltage zone in very high impedance loops (long loops), the dc feeding can be considered as a voltage source wi th zero internal resistance (r v ) . in this zone, the voltage v tip/ring is constant and the current i tip/ring depends on the load between the tip and ring lines. see figure - 5 . to avoid clipping the high level ac speech signals, a voltage reserve v res should be provided: where, v bat is the selected battery voltage, v lim is the open circuit voltage. normally, v res = 2 v. when the dc feeding is operating at the constant voltage zone, the indication bit feed_v in register lreg 21 will be set to 1, otherwise it is set to 0. figure - 2 dc feeding zones figure - 3 constant current zone resistive zone constant current zone constant voltage zone v tip-ring i tip-ring necessary voltage reserve v res v bat v tip-ring i tip-ring r i r l figure - 4 resistive zone v tip-ring i tip-ring r lin r l v res v bat v lim ? = 18 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.2.5 dc feeding characteristics configuration the dc feeding characteristic is programmable. when the dc_feed bit in register lreg5 is set to 1, the default dc feeding characteristic will be selected (see figure - 6 ). the default configuration is typically for -24 v battery volt age application. when the dc_feed bit is set to 0, the dc feeding char acteristic is determined by the coefficients written in the coe-ram. idt provides a software (cal74) that can calculate the coefficients for dc feeding. when users input the desired values for i max, i k1, v k1, i k2, v k2 and v lim, cal74 will automatically calculate the dc feeding coefficients. when these coefficient s are loaded to the coe-ram, the dc feeding characteristic wi ll meet the requirements. to reduce power consumption and ma ke the dc loop stable, it is recommended to reduce i max and keep the output resistance (r i ) less than 5 k ? when the loop is operated in the constant current zone. here is an example for short loop applications (see figure - 7 ): loop resistance < 600 ? ; i max = 25 ma; v k1 = 20 v; i k1 = 20 ma (loop current requirement) r i = |(v k1 ? 0)/(i k1 ? i max )| = |(20 ? 0)/(20 ? 25)| = 4 k ? figure - 5 constant voltage zone v tip-ring i tip-ring r l r v figure - 6 dc feeding ch aracteristics configuration figure - 7 dc feeding configuration example for short loop applications v tip-ring i tip-ring i max v lim i k1 i k2 r lin r v v k2 v k1 (25 ma) (18 v, 23 ma) (19.5 v, 16 ma) (22 v) v tip-ring i tip-ring 14ma 40 48 36 i max (25 ma) i k1 (20 ma) v k1 (20 v) r i 19 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range table - 1 lists the registers and the coe-ram locations used for dc feeding configuration. for more in formation about the coe-ram, please refer to ?5.2.5 addressing the coe-ram? on page 61 and table - 23 on page 62 . table - 1 registers and coe-ram locatio ns used for dc feeding configuration parameter register bits /coe-ram words notes dc feeding coefficients selection bit dc_feed in lreg5 dc_feed = 0: the dc feeding coefficient in the coe-ram is selected. dc_feed = 1: the dc feeding coefficient in the rom is selected (default); constant current zone indication bit feed_i in lreg21 when the dc feeding is operating at the constant current zone, the feed_i bit is set to 1, otherwise it is set to 0. resistive zone indication bit feed_r in lreg21 when the dc feeding is operating at the resistive zone, the feed_r bit is set to 1, otherwise it is set to 0. constant voltage zone indication bit feed_v in lreg21 when the dc feeding is operating at the constant voltage zone, the feed_v bit is set to 1, otherwise it is set to 0. i max dc feeding coefficients in the coe-ram programmable via the coe-ram. programmable range: 0 to 50 ma with 7% tolerance. default value (in the rom): 25 ma. i k1 programmable via the coe-ram. programmable range: 0 to 50 ma with 7% tolerance. default value (in the rom): 23 ma. v k1 programmable via the coe-ram. programmable range: 0 to 48 v with 7% tolerance. the default value (in the rom): 18 v. i k2 programmable via the coe-ram. programmable range: 0 to 50 ma with 7% tolerance. default value (in the rom): 16 ma. v k2 programmable via the coe-ram. programmable range: 0 to 48 v with 7% tolerance. default value (in the rom): 19.5 v. v lim programmable via the coe-ram. programmable range: 0 to 48 v with 7% tolerance. default value (in the rom): 22 v. 20 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.3 speech processing 3.3.1 ac transmission the signal paths for ac transmi ssion between the rslic and the codec is shown in figure - 8 . in the transmit direction, the transversal and longitudinal currents on the subscr iber line are sensed by the rslic and the corresponding voltages are fed to the codec via vtac and vl pins. the voltage signals are further processed within the codec and finally transmitted to the pcm highway. in the receive direction, the codec processes data received from the pcm highway and outputs a differential analog signal to the rslic via the acp and acn pins. the rslic then amplifies this signal and applies it to the subscriber line. 3.3.1.1 transmit path the voice signal path within the codec for one channel is shown in figure - 9 . figure - 8 signal paths for ac transmission vtac vl acp acn rslic #1 vtac1 vl1 acp1 acn1 codec pcm out (data upstream) pcm in (data downstream) transmit receive tip ring vtac vl acp acn rslic #2 vtac2 vl2 acp2 acn2 tip ring vtac vl acp acn rslic #3 vtac3 vl3 acp3 acn3 tip ring vtac vl acp acn rslic #4 vtac4 vl4 acp4 acn4 tip ring mpi or gci interface transmit path receive path figure - 9 voice signal path of the codec anti-alias filter (aaf) sigma-delta modulator (sdm) digital gain transmit (gtx) low-pass filter transmit 2nd decimation filter frequency response correction transmit (frx) high-pass filter transmit (hpf) 2nd interpolation filter digital gain receive (grx) 3rd interpolation filter impedance matching filter (imf) transhbrid balance filter (ecf) 1st interpolation filter dx1/dx2 vtac acp acn 1st decimation filter pcm encoder frequency response correction receive (frr) low-pass filter receive sigma-delta demodulator (d-sdm) smoothing filter & scf gain for impedance scaling (gis) analog gain for impedance scaling (agis) programmable filter fixed filter receive path transmit path time slot assignment time slot assignment dr1/dr2 pcm decoder analog gain receive 21 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range in the transmit path, the analog voltage from the rslic is first filtered by an anti-aliasing filter (aaf) and then is converted to a digital signal by a 1-bit sigma-delta modulator (sdm). the digital signal is down-sampled to an intermediate sample frequency to feed to the digital impedance matching filter (imf). simultaneou sly, the down-sampled signal is summed up with the output of the transhybrid balance filter (ecf). the sum signal is transmitted through the transmit gain filter (gtx) and further down-sampled to the baseband. a lowpass filter removes the unwanted signals to meet itu- t requirements and a frequency response correction filter (frx) follows to compensate for the attenuation brought up by the impedanc e matching loop. the final stage is a highpass filter (hpf) before the data is sent to the pcm encoder, where data is a-law or -law compressed. at last, the data is assigned to the selected time slot and transmitted to the pcm highway. 3.3.1.2 receive path in the receive path, the signal rece ived from the pcm highway is first passed through the time slot assignment stage before being expanded to a linear code at the baseband frequency of 8 khz by the pcm decoder. the expanded data is then up-sampled to a higher frequency before passing through the frequency re sponse correction filter (frr) that compensates for the attenuation brought up by the impedance matching loop. the compensated signal is filtered by a lowpass filter and further up-sampled to the intermedi ate frequency. the signal is then sent to the receive gain filter (grx). the output of the grx goes in two ways: one feeds to the transhybrid balance filter (ecf) and the other sums up with the output of the digital impedance matching filter (imf). this sum is then up-sampled and processed by a digital sigma-delta demodulator (d-sdm). an analog filter smooths the signal and outputs it to the rslic via the acp and acn pins. 3.3.2 programmable filters a comprehensive multi-rate si gnal process scheme with fixed/ programmable filters is applied to the ac loop of the rslic-codec chipset to optimize the performance of the line card. in addition to fully complying with the itu-t g.712 specif ications, the chipset also provides additional programmable analog/digi tal filters to match impedance, balance transhybrid, correct frequen cy response and adjust gains. all of the coefficients of the digital filters can be calculated automatically by a software (cal74) provided by idt. w hen these coefficients are written to coefficient ram, the final ac transmi ssion characteristics of the line card will meet itu-t specifications. figure - 9 shows the programmable filters in the transmit and receive paths. 3.3.2.1 impedance matching for the rslic-codec chipset, impedance matching is realized with three feedback loops in each c hannel: one analog loopback, the agis (analog gain for impedance scaling) stage, and two digital loopbacks in the programmable filters stage gi s (gain for impedance scaling) and imf (impedance matching filter). see figure - 9 for details. the analog loopback realizes the r eal part value (re z l ) of the impedance, while the digital loopbacks realize th e imaginary part value (im z l ) of the impedance. the gis and imf filter loops operate at 2 mhz and 64 khz rate respectively. by programming the filters agis, gis and imf, the ac impedance of the chipset can be set to any value inside the shadowed area in figure - 10 . figure - 10 nyquist diagram 0 300 -400 -600 600 900 1200 -200 re z l im z l possible impedance values 22 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range the analog gain for impedance sc aling (agis) can be 600 ? or 900 ? , as selected by the im_629 bit in register lreg7. the option of agis=600 ? is only applicable to loops with 600 ? equivalent impedance, while the option of agis=900 ? is applicable to all loops including those with 600 ? equivalent impedance. the agis value is set to 600 ? by default. the coefficient for the gis filter is programmed by gain for impedance scaling in the coe-ra m. it is programmable from ? 128 to +127 at increment of 1. the default value is 0. if the imf bit in lreg4 is set to 1, the imf filter is disabled. if the imf bit is set to 0, the impedance matching filter coefficient in the coe-ram is used by the imf filter. refer to table - 23 on page 62 for the coefficient ram mapping. 3.3.2.2 transhybrid balance the rslic-codec chipset prov ides a traditional transhybrid balance filter (ecf) for each channel to improve 4-wire return loss performance. the ecf coefficient is programmable. if the ecf bit in register lreg4 is set to 1, the ecf f ilter is disabled. if the ecf bit is set to 0, the transhybrid balance filter coefficient in the coe-ram is used. 3.3.2.3 frequency response correction the frequency response correction filt ers are used to compensate for the frequency distortion caused by the impedance matching filter. the chipset provides two frequency res ponse correction fi lters per channel: one is in the transmit path (frx), the other is in the receive path (frr). the frx bit in lreg4 determines w hether the frx filter is disabled or programmed by the coe-ram. if the frx bit is set to 1, the frx filter is disabled. if the frx bit is set to 0, the coefficient for frequency response correction in the transmit path in the coe-ram is used. the frr bit in lreg4 determines w hether the frr filter is disabled or programmed by the coe-ram. if the frr bit is set to 1, the frr filter is disabled. if the frr bit is set to 0, the coefficient for frequency response correction in the receive path in the coe-ram is used. 3.3.2.4 gain adjustment for each channel, the gain in t he transmit path is adjusted by programming the digital filter gtx. the transmit gain can be up to +12 db in minimum steps of 0.05 db. if the gtx bit in lreg4 is set to 1, the default transmit gain of 0 db is selected. if the gtx bit is set to 0, the transmit gain is programmed via the coe-ram. for each channel, the gain in the re ceive path consists of analog gain and digital gain (grx). the analog gai n is fixed at 0 db. the digital gain is programmable from ? 12 db to +3 db in minimum steps of 0.05 db. if the grx bit in lreg4 is set to 1, the digital gain in the receive path will be 0 db (default value), ot herwise, it is programmed via the coe-ram. 23 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.4 ring and ring trip the rslic-codec chipset supports both internal and external ringing modes to meet different requirements. 3.4.1 internal ringing mode 3.4.1.1 internal ringing generation the chipset provides a built-in ring generator per channel that can generate balanced sinusoidal ringi ng signal without external components. the frequency, amplitude and dc offset of the ringing signal are programmable. in additi on, the ring trip detection can be performed internally by program ming the ring trip threshold. if internal ringing mode is selected, the rslic will be automatically switched to the higher battery (vbh) for ringing generation. the ringing signal generated by the codec is sent to the rslic via the dcp and dcn pins and further fed to the subscriber line by the rslic. refer to figure - 49 on page 104 for an application circui t using internal ringing. to generate a ringing signal, user s should first set the operating mode to internal ringing (the codec is set to the ring mode and the rslic is set to internal ringing mode, refer to table - 3 for details). next, calculate the coefficients of the ringing frequency, amplitude and dc offset and load the coefficients to the coe-ram (the calculation is performed by a software (cal74) prov ided by idt. when users input the frequency, amplitude and offset val ues, cal74 will calculate the coefficients automatically). then, the ringing generation will be controlled by the ring_en bit in lr eg7. in order to reduce noise and crosstalk on adjacent lines, the ringing signal will automatically start at a zero-crossing after the ring_en bit is set to 1 and stop at zero-crossing after the ring_en bit is set to 0. figure - 11 shows a balanced ringing signal generated by the chipset. 3.4.1.2 ring trip detection in internal ringing mode once the subscriber has swit ched from on-hook state to off-hook state during ringing, the ringing si gnal must be removed from the subscriber line before normal speec h begins. the recognition of an off- hook state during ringing, together with the removal of the ringing signal, is commonly referred to as ring trip. depending on the application requirements, the rslic-codec chip set offers two different ring trip methods for internal ringing mode, they are dc ring trip detection and ac ring trip detection, as selected by the rt_sel bit in lreg7. ? dc ring trip detection most applications use dc ring trip detection. by applying a dc offset voltage together with the ringing si gnal, a transversal dc loop current starts to flow when the subscriber goes off-hook. the rslic senses the dc current and supplies the corresponding sensed voltage to the codec via the vtac pin. the codec continuously integrates this voltage over one ringing period without rectifying. the result represents the dc component of the ring current. if the dc component exceeds the programmed dc ring trip threshold, the corresponding hk[n] bit (n = 0 to 3 are for channel 1 to 4 respectively) in register greg26 will be set to 1 to indicate that the loop has been of f-hook. an interrupt will be generated simultaneously if the corresponding mask bit hk_m[n] is set to 0. most of the applications use dc ri ng trip detection because it is very reliable. even with very long and noi sy lines the off-hook condition can reliably be detected within two ringing period by the dc ring trip. the dc ring trip method is selected by setting the rt_sel bit in lreg7 to 1. the dc offset voltage is programmed by the ringoffset in the coefficient ram. see table - 2 for detailed information. in dc ring trip mode, when an of f-hook event is detected, the ringing signal will stop immediately at zero -crossing. but the ring_en bit will not be cleared to 0 automatically; it should eventually be cleared by software. this automatic ring trip function speeds up the response to off- hook for time critical applications. ? ac ring trip detection for short loop applications, the dc offset can be removed from the ringing signal to increase the achiev able voltage amplitude for a given supply voltage. the ac ring trip detec tion without dc offset is realized by rectifying sensed ring current si gnal, integrating it over one ringing signal period and comparing the result with the programmed ac ring trip threshold. if the threshold is exceeded, the corresponding bit hk[n] (n = 0 to 3 are for channel 1 to 4 respectively) in register greg26 will be set figure - 11 internal balanced ringing v drop.t v dc.ring v drop.r v tp v rp v t v r v ring.pp = v tp - v rp bgnd vbh rslic tip line ring line 24 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range to 1 to indicate off-hook detected. an interrupt will be generated if the hk[n] bit is not masked. note that during a ring pause peri od, the off-hook condition can not be detected by the ac ring trip. when the off-hook condition is detected during a ring burst period, t he ringing signal will be removed automatically at zero-crossing. as the ring_en bit remains unchanged, users should clear it to 0 by software. if several telephones are in parallel with each other between the tip and ring lines, the on-hook ac current will increase. if the ac load is too large, the on-hook current of s hort loop will be larger than the off- hook current of long loop - this will possibly cause a false indication of the off-hook condition. consequently, the ac ring trip detection method should only be used in short loops (loop impedance < 1 k ? ) and low- power applications. table - 2 lists the programmable paramet ers used for internal ringing generation and ring trip detection. 3.4.2 external ringing mode the chipset can generate internal ringing signals of up to 70 vp. in applications of requiring higher ring amplitudes, external ringing signals can be used. figure - 50 on page 105 shows an application circuit that use an external ringing signal. if the rslic is set to external ringing mode (see table - 3 for details), the ringing signal from an external ring generator will be switched to the tip/ring lines thr ough an external relay during ring burst period, and will be removed during ring pause period. the codec provides two programm able io pins (io1 and io2) with relay-driving capability for each channel . they can be used to control the external ring relay without addition al components. the external ringing can be switched on/off in two different modes as described below: ? synchronous mode (this mode is available when the io1 pin is selected to control the external ring relay). in this mode, the external ringer provides a synchronous signal for the codec via the rsync pin to ensure switching the ringing signal at zero-crossing. this synchronous mode is enabled by setti ng the sync_en bit in lreg19 to 1. when the io1 pin of the codec is configured as an output (lreg20: io_c[0] = 1), the external ringing signal will be switched on the rsync edge (rising or falling) next to the c hange of the io1 pin, as illustrated in figure - 12 . the logic level of the io1 pin is set by the io[0] bit in lreg20: io[0] = 0: io1 pin is set to logic low; io[0] = 1: io1 pin is set logic high. in synchronous mode, the codec provides a hardware ring trip function to speed up the response of off-hook event. for example, if a logic low on the io1 pin starts the ringing while a logic high on this pin stops the ringing, once an off-hook event is detected during ring burst period, the io1 pin will be set to logic high automatically to remove the ringing signal although the io[0] bit remains 0. users should set the io[0] bit to 1 by software. ? asynchronous mode. if no synchr onous signal is applied to the rsync pin of the codec, or some applications need to switch the ringing signal without any delay caused by zero-crossing synchronization, the sync_en bit in lreg19 should be set to 0. in this case, the external ringing signal will be switched immediately after the corresponding io pin control bit (io[0] for the io1 pin and io[1] for the table - 2 registers and coe-ram locat ions used for internal ringing mode parameter register bits/coe-ram words notes internal ringing mode selection mpi mode: bit ring in lreg7, bits scan_en and sm[2:0] in lreg6; gci mode: bit ring in lreg7, bits scan_en and sm[2:0] in downstream c/i channel byte. ring = 1: the codec is set to ring mode scan_en = 1 and sm[2:0] = 010: the rlsic is set to internal ringing mode. internal ringing enable bit ring_en in lreg7 ring_en = 0: ring pause; ring_en = 1: ring burst. internal ringing parameters selection bit rg in lreg5 rg = 0: ringing parameters in the coe-ram are selected. rg = 1: ringing parameters (frequency, amplitude and offset) in the rom are selected (default); internal ringing frequency word ringfreq in the coe-ram programmable via the coe-ram. programmable range: 20 to 200 hz with 3% tolerance. default value (in the rom): 30 hz. internal ringing amplitude word ringamp in the coe-ram programmable via the coe-ram. programmable range: 0 to 70 vp with 1% tolerance. default value (in the rom): 40 vp. internal ringing offset voltage word ringoffset in the coe-ram programmable via the coe-ram. programmable range: 0 to 20 v with 1% tolerance. default value (in the rom): 7 v. ring trip method selection bit rt_sel in lreg7 rt_sel = 0: ac ring trip is selected; rt_sel = 1: dc ring trip is selected. ring trip threshold selection bit signaling in lreg5 signaling = 0: the ac and dc ring trip thresholds in the coe-ram are selected; signaling = 1: the ac and dc ring trip thresholds in the rom are selected (default); ac ring trip threshold word rtthld_ac in the coe-ram programmable via the coe-ram. programmable range: 0 to 20 ma with 5% tolerance. default value (in the rom): 5 ma. dc ring trip threshold word rtthld_dc in the coe-ram programmable via the coe-ram. programmable range: 0 to 20 ma with 5% tolerance. default value (in the rom): 5 ma. ring trip detection result indication bits hk[n] in greg26 indicating the ring trip detection result, ?0? means channel n+1 is on-hook while ?1? means channel n+1 is off-hook (n = 0 to 3) 25 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range io2 pin) in lreg20 is changed, irre spective of whether the ringing signal is at a zero-crossing or not. in this mode, even if the io1 pin is used to control the ring relay, it will act as a normal io pin. in other words, the hardware ring trip functi on is no longer available and the io1 pin is controlled completely by software through the codec. 3.4.2.1 ring trip detection in external ringing mode in external ringing mode, the sensed ring current signal is processed by an operational amplifier in the rslic and supplied to the codec via the rtin pin for ring trip detection. in external ringing mode, the level meter will be involved when detecting the ring trip. for detailed information about the level meter, please refer to ?3.9.4 level meter? on page 40 . to detect ring trip, the st eps below should be followed: 1. select the rtin as the input source to the dc path (lreg9: lm_sel[3:0] = 1100); 2. write the external ring trip threshold to hkthld in the coe-ram; 3. set the codec to active mode and set the rslic to external ringing mode (the chipset operat ing mode control bits are different in mpi interface and gci interface, refer to table - 3 for details); 4. the codec processes the rtin signal and compares the result with the external ring trip threshold written in hkthld in the coe- ram. if the threshold is exceeded, the corresponding hk[n] bit in greg26 (n = 0 to 3 corresponds to channel 1 to 4) will be set to 1, indicating that off-hook is detected. when detecting a ring trip, an offset voltage (about 10 to 30 mv) may be introduced by the operational amplifier mentioned above. this offset can be measured by the dc level meter and compensated by writing the corresponding compensation value to dc offset in the coe-ram. before measuring this offset voltage, make sure that no external ringing signal is applied to the tip/ ring lines. the m easuring procedure is as follows (to understand the fo llowing descriptions, users should understand the level meter first): 1. set the codec to active mode and set the rslic to external ringing mode (see table - 3 for details); 2. select the rtin as the input to the dc path of the codec (lreg9: lm_sel[3:0] = 1100); 3. in lreg8, set dc_src = 1 and lm_src = 0; 4. select the channel to be measured by setting the lm_cs[1:0] bits in greg16 accordingly; 5. set the integrating time to 001h (greg15 & greg16: lm_cn[10:0] = 001h); 6. set the shift factor (k[3:0] in lreg9); figure - 12 external ringing synchronization external ringing voltage v rsync v io1 v ring t t t t io[0] bit in lreg20 t suppose a logic low on the io1 pin starts the ringing. 26 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7. disable the rectifier (lreg10: lm_rect = 0); 8. set the gain factor as required (lreg10: lm_gf); 9. set the level meter measurement mode to once and start the measurement (greg16: lm_once = 1, lm_en = 1); 10.read the measurement result from greg17 & greg18 (16-bit); 11. right shift the 16-bit result for two bits, then the result is the offset value in the form of a 14-bit two?s complement; 12.invert each bit of the offset value and add 1 to it, write this result to dc offset in the coe-ram. 13.select this offset compensation value to be used (lreg4: dc_oft = 0); 14.restore the modified regist ers with original contents; then, the four steps mentioned abov e follow and off-hook event will be more reliably detected. table - 3 shows the registers and c oe-ram locations used for external ringing mode. table - 3 registers and coe-ram locat ions used for external ringing mode parameter register bits notes codec and rslic operating mode configuration mpi mode: bits active, scan_en and sm[2:0] in lreg6; gci mode: bit active in lreg6, bits scan_en and sm[2:0] in downstream c/i channel byte. active = 1: the codec is set to active mode scan_en = 1 and sm[2:0] = 001: the rlsic is set to external ringing mode. external ring relay control (recommended) bit io_c[0] in lreg20 bit io[0] in lreg20 io_c[0] = 1: the io1 pin is configured as an output io[0] = 0: the io1 pin is set to logic low io[0] = 1: the io1 pin is set to logic high synchronous mode enable bit bit sync_en in lreg19 sync_en = 0: asynchronous mode is selected sync_en = 1: synchronous mode is selected external ring trip detection source bit lm_sel[3:0] in lreg9 lm_ sel[3:0] = 1100: rtin is selected to the dc path for ring trip de tection external ring trip threshold word hkthld in the coe-ram if the signaling bit in lreg5 is set to 1, the external ring trip threshold in the rom is selected, otherwise the threshold written in hkthld in the coe- ram is selected. the hkthld in the coe-ram is programmable from 0 to 20 ma with 5% tolerance. the default value (in the rom) is 7 ma. note that both the off-hook detection threshold in active mode and the external ring trip threshold are written in hkthld in the coe-ram. users should change the threshold according to different conditions. external ring trip detection result indication bits hk[n] in greg26 indicating the ring trip detection result, ?0? means channel n+1 is on-hook while ?1? means channel n+1 is off-hook (n = 0 to 3). level meter configuration and result registers lreg8: lm_src, dc_src lreg9: k[3:0] lreg10: lm_gf, lm_rect greg15 & greg16 greg17 & greg18 refer to table - 17 on page 44 for details. dc offset compensation bit dc_oft in lreg4 word dc offset in the coe-ram dc_oft = 0: compensation value in word dc offset in the coe-ram is selected; dc_oft = 1: compensation value (which is 0) in the rom is selected (default). 27 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.5 supervision supervision is performed internally by the rslic-codec chipset. the rslic senses the longitudinal and transversal line currents on the ring and tip lines, and feeds the co rresponding voltages to the codec via the vl, vtac and vtdc pins for fu rther process. in this way, the signaling in the subscriber loop is monitored. 3.5.1 off-hook detection loop start signaling is the most common type of signaling. the subscriber loop is closed by the hook switch inside the subscriber equipment. for the rslic-codec chipset, the off-hook detection can be operated in two different modes as shown in table - 4 . ? active mode in this mode, both the rslic and the codec are active. the rslic senses the transversal current on the ring and tip lines, and feeds the corresponding voltage to the codec vi a vtdc pin. inside the codec, this voltage is a-to-d converted and fi ltered. the result is compared with the programmed off-hook threshold (word hkthld in the coe-ram). if the result exceeds the threshold, the bit hk[n] (n = 0, 1, 2 or 3) in register greg26 will be set to 1, i ndicating that channel n+1 is off-hook. an interrupt will be generated at the same time if the off-hook mask bit hk_m in register lr eg18 is disabled (?0?). in active mode, to detect the loop transition from off-hook to on-hook, the on-hook threshold should be used. the off-hook threshold minus a programmable hysteresis value is the on-hook threshold (as shown in figure - 13 ). the hysteresis value is pr ogrammed by hkhyst in the coe- ram. the default value is 2 ma. ? sleep mode in this mode, both the codec and the rslic are in standby mode. all of the function blocks except off-hook detection stop working. the transversal current on the ring and tip lines is sensed by a simple sense circuit and the corresponding sensed voltage is fed to an analog comparator in the codec via the vt ac pin. by comparing this sensed voltage with a fixed off-hook threshold of 2 ma, the off-hook event can be detected. once the loop goes off-hook, the whole chipset should be set to active mode by the master processor. the codec integrates a programmable debounce filter in the off- hook detection circuit to eliminat e disturbance. the transversal dc signal (which is taken as the off-hook criterion) will be filtered by this debounce filter. the dc signal with duration less than the debounce time will be ignored. as shown in figure - 14 , a four-bit debounce counter allows the debounce interval program mable from 0.125 ms to 2 ms. a 16-state up/down counter follows, resulting in the minimal debounce time ranging from 2 ms to 32 ms. the debounce interval is programmed by the db[3:0] bits in lreg11. (note: when the rslic operating mode is switching from other mode to the active mode, there mi ght be a narrow pulse of about 15 ms occurring on vtdc, resulting in a false off-hook interrupt to be generated. if this happens, please set the debounce time for off-hook detection to 15 ms or above (i.e., db[3:0] 0111b) to filter the noise pulse.) table - 5 shows the registers and coe-ram locations used for off- hook detection. table - 4 off-hook det ection in different modes chipset mode codec mode rslic mode mode control register setting active active active mpi mode: lreg6: active = 1, scan_en = 1, sm[2:0] = 000 gci mode: lreg6: active = 1; downstr eam c/i channel byte: scan_en = 1, sm[2:0] = 000 sleep standby standby mpi mode: lreg6: standby = 1, scan_en = 1, sm[2:0] = 110 gci mode: lreg6: standby = 1; downst ream c/i channel byte: scan_en = 1, sm[2:0] = 110 note: the operating mode of the codec is set by register lreg6. th e operating mode of the rslic is set by register lreg6 (for m pi mode) or downstream c/i channel byte. refer to ?6.1 operating modes? on page 87 for further details. figure - 13 hysteresis for off-hook detection i hook state indication off-hook threshold on-hook threshold hysteresis 28 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range figure - 14 debounce filter fo r off-hook/groun d-key detection table - 5 registers and coe-ram locat ions used for of f-hook detection parameter register bits/coe-ram words notes off-hook indication bits hk[3:0] in greg26 hk[n] = 0: channel n+1 is on-hook (n = 0 to 3); hk[n] = 1: channel n+1 is off-hook. mask bit for hk[3:0] bits bit hk_m in lreg18 hk_m = 0: each change of hk[3:0] bits generates an interrupt; hk_m = 1: changes of hk[3:0] bits do not generate interrupts. off-hook threshold selection bit signaling in lreg5 signaling = 0: the off-hook threshold in the coe-ram is selected. signaling = 1: the off-hook threshold in the rom is selected (default). off-hook threshold for active mode word hkthld in the coe-ram if the signaling bit in lreg5 is set to 0, the off-hook threshold for active mode is programmed by word hkthld in the coe-ram. it is programmable from 0 to 20 ma with 5% tolerance. if the signaling bit in lreg5 is set to 1, the default value of 7 ma (stored in the rom) is selected. hysteresis for off-hook detection word hkhyst in the coe-ram if the signaling bit in lreg5 is set to 0, the hysteresis for off-hook detection is programmed by word hkhyst in the coe-ram. it is programmable from 0 to 20 ma with 5% tolerance. if the signaling bit in lreg5 is set to 1, the default value of 2 ma (stored in the rom) is selected. debounce interval selection bits db[3:0] in lreg11 the interval is programmable from 0.125 ms to 2 ms in steps of 0.125 ms. the default value of db[3:0] is ?0000?, corresponding to the minimum debounce interval of 0.125 ms. q db[3:0] debounce interval (0.125 ms ? 2 ms) up/down q 16 states up/down counter 4 bit debounce counter 0 1 off-hook/ ground-key d en fs mclk en mux db[0] db[1] db[2] db[3] debounced off-hook/ ground-key 29 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.5.2 ground-key detection in applications of using ground-key signaling, the longitudinal current of the loop is used as ground-key cr iterion. the rslic senses the longitudinal current and transfers the scaled longitudinal voltage information to the codec via vl pin. an analog comparator for ground- key detection compares this voltage wi th a fixed threshold (11.8 ma). if the threshold is exceeded, the bit gk[n ] (n = 0, 1, 2 or 3) in register greg26 will be set to 1 to indica te that ground-key is detected in channel n+1. an interrupt will occur if any bit of gk[3:0] changing from 0 to 1. the gk[3:0] bits can be masked by the gk_m bit in register lreg18. the polarity of the longitudinal current is indicated by the gk_pol bit in register lreg21. each change of the gk_pol bit generates an interrupt. the gk_pol bit can be masked by the gkp_m bit in register lreg18. an application example is shown in the following: ? tip open or ring open mode in this case, the tip line or the ring line is switched to high impedance, the longitudinal current on the ring or tip line is sensed by the rslic and fed to the codec through the vl pin for testing. the longitudinal dc signal (whi ch is taken as the ground-key criterion) is also filtered by the programmable debounce filter used in off- hook detection. the dc signal with duration less than the denounce time will be ignored. the debounce interval is programmable by the db[3:0] bits in register lreg11. refer to figure - 14 for details. table - 6 shows the registers used for ground-key detection. 3.6 metering by polarity reversal the rslic-codec supports meteri ng by reversing the polarity of the voltage on the tip and ring lines. the actual polarity of this voltage is reversed by setting the rev_po l bit in register lreg19 to 1. the voltage polarity is reversed in a smooth way to avoid generating non-required ringing. users can contro l the transition time (time from start to end of polarity reversal ) by programming the built-in ramp generator. refer to "ramp generator" on page 47 for further details. table - 6 registers used for ground-key detection parameter register bits notes ground-key indication bits gk[3:0] in greg26 gk[n] = 0: no longitudinal current detected in channel n+1 (n = 0 to 3); gk[n] = 1: longitudinal current detected in channel n+1. mask bit for gk[3:0] bits bit gk_m in lreg18 gk_m = 0: each change of the gk[3:0] bits generates an interrupt; gk_m = 1: changes of the gk[3:0] bit do not generate interrupts. ground-key polarity bit gk_p in lreg21 gk_p = 0: negative ground-key threshold level active; gk_p = 1: positive ground-key threshold level active. mask bit for gk_p bit bit gkp_m in lreg18 gkp_m = 0: each change of the gk_p bit generates an interrupt; gkp_m = 1: changes of the gk_p bit do not generate interrupt. debounce interval selection bits db[3:0] in lreg11 the interval is programmable from 0.125 ms to 2 ms in steps of 0.125 ms. 30 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.7 enhanced sig nal processing besides the fundamental borscht functions, the rslic-codec chipset also provides several additional functions such as tone generation, fsk generation for call er-id and universal tone detection. these additional functions can be individually enabled or disabled according to the requirements of applications. 3.7.1 tone generator the codec provides two tone generators for each channel: tone generator 1 (tg1) and tone generator 2 (tg2). they can be used to generate signals such as a test t one, dtmf, dial tone, busy tone, congestion tone and caller-id alerting tone etc., and output them to the rslic via the acp and acn pins. the tg1 and tg2 of each channel can be enabled by setting bits tg1_en and tg2_en in register lreg7 to 1, respectively. if the tg bit in register lreg4 is set to 1, the default frequency and amplitude values in the rom are selected for tone generators (default: tg1amp = 0.94 v, tg1freq = 852 hz, tg2amp = 0.94 v, tg2freq = 1447 hz). otherwise, the frequency and amplitude values of tg1 and tg2 are programmed by the coe- ram. the frequency and amplitude coefficients can be calculated, respec tively, by the following formulas: f<2000 hz, frequency coefficient = 8191 ? cos(f/8000 ?2?) f>2000 hz, frequency coefficient = 16384 - 8191 ? cos(f/8000 ?2?) amplitude coefficient = a ? 8191 ? sin(f/8000 ?2?) herein, 'f' is the desired frequency of the tone. 'a' is the scaling parameter for the tone amplitude. the range of 'a' is from 0 to 1. a = 1, corresponding to the maximum amplitude, 1.57 (v); a = 0, corresponding to minimum amplitude, 0 (v). it is a linear relationship between 'a' and the amplitude, which means if a = (0 < < 1), the amplitude will be 1.57 ? (v). the frequency is programmable from 25 hz to 3400 hz. the tolerance is as follows : f < 200 hz, tolerance < 3 % ; f > 200 hz, tolerance < 1.5 % . the amplitude and frequency coefficients of the tone signal can be calculated by the cal74 software automatically. refer to table - 7 for more information about registers and coe-ram used for tone generators. note that when using the dual to ne generators, users must write 2000h (high byte: 20h; low byte: 00h ) to block2 word4 of the coe- ram to ensure proper operation. 3.7.1.1 dtmf generation dual tone multi-frequency (dtmf) is a signaling scheme using voice frequency tones to signal diali ng information. a dtmf signal is the sum of two tones, one from the low frequency group (697 - 941 hz) and one from the high frequency group ( 1209 - 1633 hz), with each group containing four individual t ones. this scheme allows 16 unique combinations. ten of these codes represent the numbers from zero through nine on the telephone keypad, the rest six codes ( ? , #, a, b, c, d) are reserved for special signaling. the buttons are arranged in a matrix, with the rows determining the low group tones, and the columns determining the high group tone for each button. based on the scheme described in the preceding paragraph, a dtmf signal can be generated by the two tone generators. by programming the amplitude and frequency of the tone generators through mpi or gci interface, the 16 standard dtmf pairs can be generated independently in each channel. the generated dtmf tone signals meet the frequency variation to lerances specified in the itu-t q.23 recommendation. 3.7.2 fsk generation for caller id the rslic-codec chipset provides an optimized fsk generator for sending caller id information. differ ent countries use different standards to send caller id information by f sk codes. the fsk modulation of the rslic-codec chipset is compatible with the most common standards: bell 202 and itu-t v.23. table - 8 shows the modulation characteristics of these two standards. table - 7 registers and coe-ram lo cations used for tone generation parameter register bits/coe-ram words notes tg frequency and amplitude coefficients selection bit tg in lreg4 tg = 0: the frequency and amplitude coefficients in the coe-ram are selected for the tone generators; tg = 1: the frequency and amplitude coefficients in the rom are selected for the tone generators (default); tg1 enable/disable bit bit tg1_en in lreg7 tg1_en = 0: tg1 is disabled. tg1_en = 1: tg1 is enabled. tg1 amplitude coefficient word tg1amp in the coe-ram the amplitude is programmable from 0 v to 1.57 v with 1% tolerance. the default amplitude (in the rom) is 0.94 v. tg1 frequency coefficient word tg1freq in the coe-ram the frequency is programmable from 25 to 3400 hz. the tolerance is 3% (f<200 hz) or 1.5% (f>200 hz). the default frequency (in the rom) is 852 hz. tg2 enable/disable bit bit tg2_en in lreg7 tg2_en = 0: tg2 is disabled tg2_en = 1: tg2 is enabled tg2 amplitude coefficient word tg2amp in the coe-ram the amplitude is programmable from 0 v to 1.57 v with 1% tolerance. the default amplitude (in the rom) is 0.94 v. tg2 frequency coefficient word tg2freq in the coe-ram the frequency is programmable from 25 to 3400 hz. the tolerance is 3% (f<200 hz) or 1.5% (f>200 hz). the default frequency (in the rom) is 1447 hz. 31 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range generally, the transmission of the f sk signal starts with a seizure signal, which is a string of '01' pa irs. then a mark signal which is a string of ?1? follows. the caller id information comes after the mark signal. between two bytes of the call er id information, a flag signal which is a string of '1' is inserted so that the receiver can have enough time to process the received bytes. the transmission sequence of the fsk signal is shown in figure - 15 . the lengths of the seizure si gnal, mark signal, flag signal and caller id data are programmabl e by register greg21, greg22, greg19 and greg20, respectively. the codec provides total 64 bytes ram (called fsk-ram) to store the caller id information. if the length of the information is less than 64 bytes, all information bytes can be written to the fsk-ram at one time. if the length of the information is longer than 64 bytes, the information should be divided into two or more segments according to its actual length (each segment 64 bytes). write one segment to the fsk-ram at one time. when this segment has been sent out, the fsk-ram can be updated with the next segment. repeat the same operation until all segments have been sent out. refer to ?5.2.4 addressing the fsk- ram? on page 60 for further details on accessing the fsk-ram via mpi or gci interface. the fsk generator is controlled by register greg23, as described in the following: - bit fsk_en. this bit is used to enable or disable the fsk generator. the fsk_en bit must be set to 1 to enable the fsk generator before fsk transmission starts. when the transmission is finished, the fsk_en bit should be set to 0 to disable the fsk generator. - bits fsk_cs[1:0]. these two bits are used to select a channel to send fsk signal (the fsk generator is shared by four channels). - bit fsk_bs. this bit is used to select one of the two fsk modulation standards bell 202 and itu-t v.23. - bit fsk_ts. this bit is used to start the fsk transmission. once the fsk_ts bit is set to 1, the fsk generator begins to send the data written in the fsk-ram automati cally, following the procedure shown below: step 1: start, send seizure signal; step 2: send mark signal; step 3: send one start bit (0), one byte of data in the fsk-ram, one stop bit (1), then send flag signal; step 4: check whether all data in the fsk-ram has been sent out. if it has, set the fsk_ts bit to 0 and stop, otherwise return to step 3. - bit fsk_mas. this bit determines whether the fsk generator will output a mark-after-send signal (a string of ?1?) after the data in the fsk- ram has been sent out. if total caller id information is longer than 64 bytes, the fsk_mas bit should be set to 1. after sending out one segment, the fsk generator will keep sending out a mark-after-send signal to hold the established communication channel for sending the remaining segment(s). after all segments have been sent out, the fsk_mas bit should be set to 0 so that the output of the fsk generator will be muted. once the fsk_mas bit is 0, changing it from 0 to 1 will not make the mark-after-send signal active until a new transmission starts (fsk_ts = 1). if total caller id information is less than 64 bytes, the fsk_mas bit should be set to 0 so that the output will be muted after all information has been sent out. note that the caller id information is read from or written to the fsk- ram via mpi or gci interface with msb first; but the fsk codes are sent out by the fsk generator through the selected channel with lsb first. table - 8 fsk modulation characteristics characteristic itu-t v.23 bell 202 mark (logic 1) 1300 3 hz 1200 3 hz space (logic 0) 2100 3 hz 2200 3 hz modulation fsk transmission rate 1200 6 baud data format serial binary asynchronous figure - 15 fsk signal transmission sequence seizure signal mark signal data byte flag signal fsk_ts transmit signal in this example, seizure length = 32(d) (fsk_sl[7:0] = 16(d)); mark length = 32(d) (fsk_ml[7:0] = 32(d)); flag length = 8(d) (fsk_fl[7:0] = 8(d)); data length = 4(d) (fsk_dl[7:0] = 4(d)). start bit stop bit data byte flag signal start bit stop bit data byte flag signal start bit stop bit data byte flag signal start bit stop bit 32 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range table - 9 shows the configuration and c ontrol registers used for the fsk generator. refer to figure - 16 on page 33 for a recommended programming flow chart for fsk generation. table - 9 registers and fsk-ra m used for the fsk generator parameter register bits/fsk-ram notes flag length bits fsk_fl[7:0] (greg19) the length of the flag signal is programmable from 0 to 255 (bits). data length bits fsk_dl[7:0] (greg20) data length is the number of the caller id data bytes written in the fsk-ram. the valid data length is 0 to 64 (bytes). seizure length bits fsk_sl[7:0] (greg21) seizure length is the number of ?01? pairs that represent the seizure signal. the length of the seizure signal is two times of the value specified in greg21. that means, seizure length can be up to 510 pairs. mark length bits fsk_ml[7:0] (greg22) the length of the mark signal is programmable from 0 to 255 (bits). transmit start bit fsk_ts in greg23 fsk_ts = 1: fsk transmit start. the fsk_ts bit will be cleared to 0 automatically after the data in the fsk-ram is completely sent out. mark after send bit fsk_mas in greg23 after the data in the fsk-ram is sent out, if fsk_mas = 1, the fsk generator sends out a mark-after-send signal (a string of ?1?), otherwise, the output of the fsk generator is muted. fsk modulation standard selection bit fsk_bs in greg23 fsk_bs = 0: bell 202 is selected; fsk_bs = 1: itu-t v.23 is selected. fsk generator enable bit fsk_en in greg23 fsk_en = 0: fsk generator is disabled; fsk_en = 1: fsk generator is enabled. fsk channel selection bits fsk_cs[1:0] in greg23 select one of the four channels to send the caller id data. fsk data ram fsk-ram total 64 bytes 33 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range figure - 16 recommended programming flow chart for fsk generation read greg23 fsk_en = 1 ? fsk_ts = 0 ? fsk_en = 1 set seizure length (greg21) set mark length (greg22) set flag length (greg19) total caller id data =< 64 bytes ? set data length (greg20) write cid data into fsk-ram in greg23: - select a channel by setting bits fsk_cs[1:0]; - select a standard by setting bit fsk_bs; - fsk_mas = 0; - fsk_ts = 1 set the length of the caller id data to be sent at this time (greg20) write the caller id data to be sent at this time to the fsk-ram finish sending all caller id data ? fsk_mas = 0 fsk_en = 0 end seizure length = 0 mark length = 0 end start n y fsk_ts = 0 ? fsk_en = 0 y n y n y n y n fsk_ts = 0 ? y n in greg23: - select a channel by setting bits fsk_cs[1:0]; - select a standard by setting bit fsk_bs; - fsk_mas = 1; - fsk_ts = 1 34 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.7.3 universal tone detection (utd) 3.7.3.1 introduction the rslic-codec chipset provides optimized solution not only for voice transmission, but for modem data transmission. the performance of the latter is becoming a key per formance for the increasing internet access and other data applications. t he chipset?s universal tone (fax/ modem tone) detection allows the use of modem-optimized filter for v.34 and v.90 connections. the codec provides an integrated universal tone detection (utd) unit per channel to detect fax and m odem tones from the transmit or receive path. the utd unit can detect tone signals whose frequencies are between 1500 hz and 2600 hz. if a fax or modem tone is detected, which means that a modem connection is about to be established , the lowpass filter (see figure - 9 on page 20 ) characteristic is changed to a modem-optimized one. if the modem data transmission is completed, the lowpass filter characteristic will be switched back to the vo ice-optimized one for voice data transmission. with this mechanism implemented in the chipset, the optimum modem transmission rate can always be achieved. the characteristic of the lowpass filter can be changed by software. if the v90 bit in register lreg5 is set to 1, this filter will be configured for v90 connections (modem-opt imized), otherwise it will be configured for v34 connections (voice-optimized). 3.7.3.2 utd principle as shown in figure - 17 (utd functional block diagram), the input signal from transmit or receive path is first filtered by a programmable bandpass filter and a programmable bandstop filter separately. the in- band (upper path) and out-of-band (l ower path) signals are then separated from each other and the corresponding absolute values are calculated. the two calculated results are sent to two integrators, respectively. finally, the evaluati on logic block determines whether a tone is detected by comparing the in-band level with the out-of-band level. if a tone has been detected in the receive or transmit path, the utd_ok bit in lreg21 will be set to 1 and an interrupt will be generated. the utd_ok bit will be set to 1 if all the following conditions hold for a time span of at least a recognition time (rtime, programmable by lreg14) without occurring break s longer than a recognition break time (rbrktime, programmable by lreg15): ? the in-band signal level is higher than out-band signal level. ? the in-band signal level is higher than the floor threshold (programmable by word utdt hld_floor in the coe-ram). ? the in-band signal level is lower than the ceiling threshold (programmable by word utdthld_ceiling in the coe-ram). figure - 18 shows an example of utd recognition timing. the utd_ok bit will be reset to 0 if one of the preceding conditions is violated for at least a time span of an end detection time (etime, programmable by lreg16) during wh ich the violation does not cease for at least an end detection break time (ebrktime, programmable by lreg17). refer to figure - 19 for an example of utd tone end detection timing. figure - 17 utd functional diagram |x| |x| integrator evaluation logic signal in programmable bandpass filter programmable bandstop filter integrator detection result 35 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range figure - 18 example of utd recognition timing figure - 19 example of utd tone end detection timing rbrktime rtime rbrktime tone utd-ok rtime utd-ok t t t ebrktime etime ebrktime etime utd-ok tone utd-ok t t t 36 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.7.3.3 utd programming table - 10 shows the registers and coe-ram locations used for the utd unit. the utd unit can be enabled or di sabled individually for each channel by the utd_en in regist er lreg8. the utd_src bit in lreg8 determines whether the signal from transmit or receive path is detected. the rtime, rbrktime, etime and ebrktime of the utd are programmed by lreg14, lreg15, lreg16 and lreg17, respectively. if the utd bit in lreg5 is set to 0, the coefficients of the bandpass and the bandstop filters and the thresholds of the signal are programmable via the coe-ram. t he center frequencies of the two filters should be the same. the center frequency can be programmed from 1500 hz to 2600 hz. the bandwidth s of the two filters are also programmable. the ceiling and floor thresholds of the signal can be programmed from ? 30 dbm to 0 dbm in minimum steps of 0.2 dbm. idt provides a software (cal74) to calculate the filter and threshold coefficients. when users input t he desired center frequency, bandwidth for the two filters and ceiling threshold, floor threshold for the signal, the software will automatically calculate all the coefficients for the utd unit. after loading these coefficients to t he coe-ram, the performance of the utd unit will meet the users? requirements. refer to table - 23 on page 62 for the coe-ram mapping. if the utd bit is set to 1, the filter coefficients and the thresholds in the rom are used. these val ues are used by default. see table - 10 for details. table - 10 registers and coe- ram locations used for utd parameter register bits/coe-ram words notes utd unit enable bit utd_en in lreg8 utd_en = 0: the utd unit is disabled; utd_en = 1: the utd unit is enabled. utd source selection bit utd_src in lreg8 utd_src = 0: signal from receive path is detected; utd_src = 1: signal from transmit path is detected. utd result indication bit utd_ok in lreg21 utd_ok = 0: no fax/modem tone has been detected; utd_ok = 1: fax/modem tone has been detected. utd rtime bits utd_rt[7:0] (lreg14) recognition time, programmable from 0 to 4000 ms. the default value is 304 ms. utd rbrktime bits ut d_rbk[7:0] (lreg15) recognition break time, programmable from 0 to 1000 ms. the default value is 100 ms. utd etime bits utd_et[7:0] (lreg16) end detection time, programmable from 0 to 1000 ms. the default value is 256 ms. utd ebrktime bits utd_ebrk[7:0] (lreg17) end detection break time, programmable from 0 to 255 ms. the default value is 100 ms. utd filter coefficients and signal thresholds selection bit utd in lreg5 utd = 0: the signal thresholds and filter coefficients written in the coe- ram are selected. utd = 1: the signal thresholds and filter coefficients in the rom are selected (default); utd bandpass filter coefficient utd bandpass filter coefficient in the coe-ram the center frequency is programmable from 1500 hz to 2600 hz. the default center frequency and bandwidth (in the rom) are 2100 hz and 60 hz respectively. utd bandstop filter coefficient utd band stop filter coefficient in the coe-ram the center frequency is programmable from 1500 hz to 2600 hz. the default center frequency and bandwidth (in the rom) are 2100 hz and 230 hz respectively. utd signal ceiling threshold utdthld_ceiling in the coe-ram programmable from ? 30 dbm to 0 dbm in minimum steps of 0.2 dbm. the default value (in the rom) is ? 6 dbm. utd signal floor threshold utdthld_floor in the coe-ram programmable from ? 30 dbm to 0 dbm in minimum steps of 0.2 dbm. the default value (in the rom) is ? 18 dbm. 37 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 3.8 three-party conference 3.8.1 introduction the rslic-codec chipset provi des a three-party conference facility on the pcm interface in mpi m ode only. with this facility, either an external three-party c onference or an internal three-party conference can be held without additional hardware. figure - 20 shows the conference block diagram. when an external conference mode is selected (greg7: confx_en=1), the chipset acts as a server for three external ca lling partners (b, c and d) to hold a conference with each other. when an internal conference mode is selected (greg7: conf_en=1), a conference can be held between an internal calling partner (s) and two external calling partners (b and c). the internal calling partner is a s ubscriber connected to one of the four channels of the local codec. the external calling partners do not need any conference facility, for the chipset performs all the functions required by a conference for them. the three-party conference facility consists of adders, gain stages, pcm configuration registers and a conf erence control register. the voice data in the receive time slots of any two partners is added by the adder and sent to the transmit time slot of the third partner. the registers greg9, greg11 and greg13 are used to select transmit pcm highway and time slot for the thr ee partners. the registers greg10, greg12 and greg14 are used to select receive pcm highway and time slot for the three partners. to avoid overflow of the sum signals, a programmable gain stage (g) is us ed. the gain is programmed by greg8. the conf_en and confx_en bits in greg7 are used to select the internal and external c onferences respectively. if internal conference is selected, the conf_cs[ 1:0] bits in greg7 are used to select one of the four channels of the local codec to attend the conference. both a/-law compressed (8-bit) and linear (16-bit 2?s complement) voice data can be transferred in a three-party conference. if compressed data format is selected, at least 7 time slots are needed in the transmit/ receive pcm highway to perform a three-party conference and use the four local channels at the same time (three time slots for partners b, c and d, four time slots for local channel 1 to 4). so the lowest bclk frequency should be 512 khz, correspondi ng to 8 time slots available. 3.8.2 pcm interface configuration the pcm interface can be configured to work in different mode as shown in table - 11 . the p_down bit in lreg6 is used to power down the specify channel of the codec. when all four channels of the chipset are powered down, no data is transferred via the pcm highways. the p_down bit together with the conf_en and confx_en bits control the conference behavior and the pcm line drivers. figure - 20 conference block diagram r3 r2 r4 x3 x4 x2 d c b d c b + g 0 1 conf_en=0 g + + g 0 1 conf_en=0 - - - + + + a a subscriber s pcm highway1 pcm highway2 g: gain stage (gain factor) programmed by greg8 x1 - x4: 4 time slots in transmit pcm highway r1 - r4: 4 time slots in receive pcm highway a, b, c, d: external calling partners s: internal calling partner, which is connected to one of the four channels of the local codec. r1 x1 38 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range ?pcm off when the chipset is just reset, or in the power down state, no data is transferred via the pcm highways. al so when selecting new time slots, it's recommended to switch off t he pcm line drivers by setting the corresponding p_down bit to 1, conf_en bit and confx_en bit to 0. ? pcm active this is the normal operating mode without conference. only time slots r1 and x1 are used. voice data is transferred from an external subscriber a to an internal subscriber s. ? external conference in this mode the chipset acts as a conferencing server for subscribers b, c and d. these thr ee partners may be controlled by any device connected to the pcm highways. to reduce the power consumption, the channels of the local codec can be powered down if they are not being used. ? external conference + pcm active as in the external conference mode, any external three-party conference is supported in this mode. at the same time, if the channels of the local codec are powered on (a ctive), the subscribers connected to the corresponding channels can make normal phones calls. ? internal conference if the subscriber s is one of the conference partners, the internal conference mode should be selected. then, a three-party conference can be held between the internal part ner s and the external partners b and c. in this mode, the codec channel which the partner s is connected must be powered on. 3.8.3 control the active pcm channels table - 12 shows the register configur ation for the transmit pcm channels. for details refer to ?4.1.2 pcm interface? on page 51 . table - 11 conference mode configuration bits receive time slots transmit time slots mode p_down (lreg6) conf_en (greg7) confx_en (greg7) r1 r2 r3 r4 x1 x2 x3 x4 subscriber s pcm off 1 0 0 - - - - off off off off off pcm active 00 0a---soffoffoffa external conference 1 0 1 - b c d off g(c+d) g(b+d) g(b+c) off external conference + pcm active 0 0 1 a b c d s g(c+d) g(b+d) g(b+c) a internal conference 0 1 0 - b c - off g(c+s) g(b+s) off g(b+c) table - 12 active pcm channel configuration bits control bits transmit pcm time slot p_down (lreg6) conf_en (greg7) confx_en (greg7) l_code (greg3) x1 x2 x3 x4 10 0 - -- - - 00 00pcm- - - 00 01hb lb- - - 01 00-pcmpcm- 0 1 0 1 - hb lb hb lb - 0 1 0 0 pcm pcm pcm - 0 1 0 1 hb lb hb lb hb lb - 10 10-pcmpcmpcm 1 0 1 1 - hb lb hb lb hb lb 0 0 1 0 pcm pcm pcm pcm 0 0 1 1 hb lb hb lb hb lb hb lb 1 1 1 0 - pcm pcm pcm 1 1 1 1 - hb lb hb lb hb lb 0 1 1 0 pcm pcm pcm pcm 0 1 1 1 hb lb hb lb hb lb hb lb 39 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range notes: in table - 11 and table - 12 : 1. the ?p_down? bit (in register lreg6) is used to power down the corresponding channel of the codec: p_down = 1, power down; p_ down = 0, power on. 2. the ?l_code? bit (in register greg3) is used to select the pcm data format: l_co de = 1, linear code; l_code = 0, a/-law comp ressed code. 3. 'pcm' means pcm compressed data (a-law/-law). 4. hb and lb represent the high byte and low byte of the linear data respectively. 5. modes in rows with gray background are for testing purpose only. 40 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range 3.9 itdf 3.9.1 introduction subscriber lines are often affected by many types of failures, e.g., short circuits, broken lines, leak age currents, noise etc. service providers must be able to perform li ne tests and respond quickly if there are any failures. traditional line cards solutions us ually need external relays and test equipment to accomplish line tests. the rslic-codec chipset provides integrated test and diagnosis functions (itdf) that can monitor and diagnose line faults and line card devi ce failures without test relays or test equipment. with the itdf im plemented, the chipset increases the test possibilities, reduces the test ing time and cost and provides more flexibility for system manufacturers and service providers over traditional solutions. 3.9.2 diagnosis and test functions a set of signal generators and features are implemented in the chipset to accomplish various diagnosis functions. the codec generates an appropriate test signal, applie s it to the loop, measures the resulting voltage or current signal level and reports the result to a master microprocessor. all the tests can be initiated by the microprocessor and results can be read back very easily. by monitoring the subscriber loop, the itdf might prevent any problem s caused by the subscriber line or line equipment from affecting the service. the chipset can accomplish the following test and measurement functions: ? loop resistance ? leakage current tip/ring ? leakage current tip/gnd ? leakage current ring/gnd ? ringer capacitance ? line capacitance ? line capacitance tip/gnd ? line capacitance ring/gnd ? external voltage measurement tip/gnd ? external voltage measurement ring/gnd ? external voltage measurement tip/ring ? measurement of ringing voltage ? measurement of line feed current ? measurement of supply voltage vdd of the codec ? measurement of transversal and longitudinal currents 3.9.3 integrated signal generators the signal generators available on the chipset are as follows: ? constant dc voltage generation (programmable ringing dc offset voltages); ? two independent tone generators (tg1 and tg2) per channel (used to generate dtmf signal and various test tones. please refer to ?3.7.1 tone generator? on page 30 for details); ? ramp generator (used for capacitance measurement, refer to page 47 for details); ? ring generator (used to generat e an internal balanced ringing signal. refer to ?3.4.1.1 internal ringing generation? on page 23 for details). 3.9.4 level meter an on-chip level meter together with the signal generators mentioned accomplishes all test and diagnosis functions. figure - 21 on the following page shows the entire level meter block diagram. 3.9.4.1 level meter source selection the level meter is shared by all four channels. the lm_cs[1:0] bits in register greg16 select one of the channels for level metering. for each channel, there are one ac si gnal source and ten dc signal sources to be selected. the lm_s rc and dc_src bits in register lreg8 and the lm_sel[3:0] bits in register lreg9 make the selection. see table - 13 for details. attention: the vtdc is selected as the level meter source by default. when the codec works in acti ve mode, it automatically adjusts the dc feeding according to the dc voltage on the vtdc pin. so, selecting inputs vl, io3, io4, io3-io 4, dcn-dcp or vdd/2 as the level meter source may disturb the dc feeding regulation and cause problems in the dc loop. to avoid this, users can freeze the output of the dc loop before selecting these in puts as the sources by setting the active bit in lreg6 to 0. ? ac level meter if the lm_src bit in register lreg8 is set to 1, the ac signal in the transmit path (vtac) is selected for level metering. the ac level meter can measure t he voice signal at 8 khz while the active voice signal is being processed (see figure - 21 ). after being pre- filtered, a/d converted and decimated, the signal can be filtered by a programmable filter. the lm_filt bit lreg8 determines whether the filter is enabled. if the filter is enabled, the lm_notch bit in lreg8 determines which filter characterist ic (notch or bandpass) is selected. lm_filt = 0: the filter is disabled (normal operation); lm_filt = 1: the filter is enabled; lm_notch = 0: notch filter characteristic is selected; lm_notch = 1: bandpass filter c haracteristic is selected. the filter coefficients can be from the coe-ram or from the rom, as selected by the lm_n and lm_b bits in lreg5. lm_n = 0: the coefficient in the coe-ram is used for the notch filter; table - 13 level meter source selection lm_src dc_src lm_sel[3:0] level meter source 1 x xxxx ac signal in transmit path (vtac) 0 0 xxxx digital dc signal 0 1 0000 dc voltage on vtdc (default) 0 1 0100 dc output voltage on dcn-dcp 0 1 1001 dc voltage on vl 0 1 1010 voltage on io3 0 1 1011 voltage 0n io4 0 1 1100 voltage on rtin 01 1101vdd/2 0 1 1110 offset voltage (vcm is selected) 0 1 1111 voltage on io4-io3 41 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range lm_n = 1: the coefficient in the rom is used for the notch filter; lm_b = 0: the coefficient in the coe-ram is used for the bandpass filter; lm_b = 1: the coefficient in the rom is used for the bandpass filter; the center frequency of the notch/bandpass filter is programmable from 300 hz to 3400 hz. the default center frequency is 1014 hz. the quality factor (q) is fixed to 5. t he filter coefficients are automatically calculated by a software (cal74) prov ided by idt. when users input the center frequency, this software will ca lculate the coefficient for the notch or bandpass filter. by loading the coef ficients to the coe-ram of the codec, the filter characteristic can meet the requirements. refer to table - 23 on page 62 for the coe-ram mapping. ? dc level meter if the lm_src bit in register lreg8 is set to 0, the dc level meter is selected to perform the measurem ent. the dc signal source can be from transmit or receive path dependi ng on the dc_src bit in register lreg8: dc_src = 0: dc signal (digital) from receive path is selected; dc_src = 1: dc signal from transmit path is selected. there are a total of nine dc signal sources in the transmit path. they are specified by the lm_sel[3:0] bi ts in register lreg9. refer to table - 13 for details. as figure - 21 shows, the selected signal from dc transmit path is filtered, a/d converted and decimated. the effective sampling rate after the decimation stage is 8 khz. the offset register here is used to compensate for the current and voltage offset errors. see ?3.9.6.1 offset current measurement? on page 45 and ?3.9.6.7 voltage offset measurement? on page 49 for details. 3.9.4.2 level meter gain filter and rectifier the selected signal from the ac or dc path is further processed by a programmable digital gain filter. the add itional gain factor is either 1 or 16 depending on the lm_gf bit in register lreg10: lm_gf = 0: no additional gain factor; lm_gf = 1: additional gain factor of 16. the lm_gf bit should be set to 0 unless the tested signal is small enough. a rectifier follows to change the minus signal to plus signal. it can be enabled or disabled by the lm_rec t bit in register lreg10: lm_rect = 1: rectifier enabled; lm_rect = 0: rectifier disabled. figure - 21 level meter block diagram filter a/d 2 mhz decimation bandpass/ notch filter rectifier shift factor integrator result register vtac mux a/d 1 mhz decimation vtdc vl io3 io4 vdd/2 filter offset register io4-io3 mux vrdc rtin mux comparator threshold register 16/1 channel1 channel2 channel3 channel4 mux bit dc_src in lreg8 bits lm_filt and lm_notch in lreg8 bits lm_b and lm_n in lreg5 lm bandpass filter coefficient lm notch filter coefficient vcm bits lm_sel[3:0] in lreg9 bit lm_src in lreg8 bits lm_th[2:0] in lreg10 bits k[3:0] in lreg9 bits lm_en and lm_once in greg16 bits lm_cn[10:0] in greg15 and greg16 bit lm_rect in lreg10 bit lm_gf in lreg10 bit lm_ok in lreg21 bits lm_cs[1:0] in lreg10 dc path ac path bit othre in lreg10 from transmit from receive bits lmrl[7:0] in greg17 bits lmrh[7:0] in greg18 bit dc_oft in lreg4 word dc offset in the coe-ram digital dc signal dcn-dcp 42 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range 3.9.4.3 level meter integrator an integrator is used to accumulate and sum up the signal values over a preset period. the ac cumulation period (count number) is programmable from 0 to 255.875 ms in steps of 0.125 ms, by the bits lm_cn[10:0] in registers greg15 and greg16. the integrator can be configured to run once or continuous ly by the lm_once bit in greg16: lm_once = 0: integrator runs continuously; lm_once = 1: integrator runs once. in continuous mode, the integrator starts to accumulate the samples after the lm_en bit in register greg16 is set to 1. when the count number is reached, which means that once integration is finished, the lm_ok bit in lreg21 will be set to 1 and an interrupt will be generated. the next integration starts right after the previous integration is finished, and the lm_ok bit will be automatically reset after 125 s. the integrator runs continuously in this way and will not stop unless the lm_en bit is set to 0. figure - 22 shows the continuous measurement sequence. in single mode, the integrator works only once after each initiation (lm_en = 1). once the integration is finished, the lm_ok bit will be set to 1 and will not be reset until the lm_en bit is set to 0. to start a new integration, the lm_en bit must be changed from 0 to 1. the single measurement sequence is illustrated in figure - 23 . figure - 22 continuous measurem ent sequence (ac & dc level meter) greg16: lm_en lreg21: lm_ok 125 s 125 s 125 s int. period int. period int. period int. period greg16: lm_once = 0 read result greg17 & greg18 read result greg17 & greg18 read result greg17 & greg18 figure - 23 single measurement sequence (ac & dc level meter) int. period int. period greg16: lm_en greg16: lm_once = 1 start new measurement lreg21: lm_ok read result (greg17 & greg18) 43 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range in both continuous and single modes, the level meter result lm value is sent to registers greg17 & gr eg18 after every integration period. to calculate the measured signal level, a factor lm result is defined as: the number of samples n samples for the integrator is calculated by: n samples = lm_cn where, lm_cn is the level me ter count number (set by bits lm_cn[10:0] in regist ers greg15 & greg16). then the signal level can be calculated by the following formula: where, k int is the selected shift factor. refer to ?3.9.4.5 level meter shift factor? for details. 3.9.4.4 level meter result register the level meter result is a 16-bit 2's complement. the low byte and high byte of it are stored in registers greg17 and greg18 respectively. table - 14 shows the range of the result value. 3.9.4.5 level meter shift factor as the level meter result is a 16-bit 2's complement while the integration width is 27 bits, a shift fa ctor is necessary to avoid generating an overflow in result registers and make the results with maximum accuracy. the shift factor k int is programmed by register lreg9. see table - 15 for details. 3.9.4.6 level meter threshold setting once the level meter result is latched in the result registers, it will be compared with a programmable thres hold. if the absolute value of the result exceeds the threshold, the ot hre bit in register lreg10 will be set to 1. this threshold is a percentage value of the full scale (see table - 14 ). it is programmed by the lm_th[2: 0] bits in lreg10. refer to table - 16 for details. table - 14 level meter result value range negative value range positive value range ? full scale + full scale 0x8000 0xffff 0 0x7fff ? 32768 ? 1 0 + 32768 lm result lm value 32768 ---------------------- - = udbm 0 20 lm result 2 k int n samples ----------------------------------------------- ?? ?? log 3.14 + = table - 15 shift factor selection k[3:0] bits in lreg9 shift factor 0000 k int = 1 0001 k int = 1/2 0010 k int = 1/4 0011 k int = 1/8 0100 k int = 1/16 0101 k int = 1/32 0110 k int = 1/64 0111 k int = 1/128 1000 k int = 1/256 1001 k int = 1/512 1010 k int = 1/1024 1011 to 1111 k int = 1/2048 table - 16 level meter threshold setting lm_th[2:0] in lreg10 threshold lm_th[2] lm_th[1] lm_th[0] 0000% 00112.5% 01025.0% 01137.5% 10050.0% 10162.5% 11075.0% 11187.5% 44 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range table - 17 sums up the registers and coe-ram locations used for the level meter. table - 17 registers and coe-ram lo cations used for the level meter parameter register bits/coe-ram words notes level meter channel selection lm_cs[1:0] bits in greg16 the lm_cs[1:0] bits determine the signal from which channel to be level metered. level meter source selection lm_src and dc_src bits in lreg8 lm_sel[3:0] bits in lreg9 refer to table - 13 for details. level meter shift factor selection k[3:0] bits in lreg9 refer to table - 15 for details. level meter count number (integration time) selection lm_cn[10:0] bits in greg15 & greg16 the lm_cn[10:0] bits is programmable from 0 to 7ffh, corresponding to the integration time of 0.125 ms to 255.875 ms. level meter result lmrl[7:0] bits in greg17 (low byte) lmrh[7:0] bits in greg18 (high byte) see table - 14 for details. level meter threshold threshold selection: lm_th[2:0] bits in lreg10 over threshold indication: othre bit in lreg10 refer to table - 16 for details on threshold selection. once the selected threshold is exceeded, the othre bit will be set to 1. level meter bandpass/notch filter configuration lm_filt and lm_notch bits in lreg8 lm_filt = 0: bandpass/notch filter is disabled; lm_filt = 1: bandpass/notch filter is enabled; lm_notch = 0: notch filter characteristic is selected; lm_notch = 1: bandpass filter characteristic is selected. level meter bandpass/notch filter coefficient selection lm_b and lm_n bits in lreg5 lm_b = 0: the coefficient in the coe-ram is selected for the bandpass filter; lm_b = 1: the coefficient in the rom is selected for the bandpass filter (default); lm_n = 0: the coefficient in the coe-ram is selected for the notch filter; lm_n = 1: the coefficient in the rom is selected for the notch filter (default). lm bandpass filter coefficient lm bandpass filter coefficient in the coe-ram when lm_b = 1, this coefficient will be selected for the bandpass filter. lm notch filter coefficient lm notch filter coefficient in the coe-ram when lm_n = 1, this coefficient will be selected for the n otch filter. level meter enable lm_en bit in greg16 a logic high in this bit starts a level meter measurement while a logic low stops the measurement. indication of level meter measurement completed lm_ok bit in lreg21 once the measurement is finished, the lm_ok bit will be set to 1. level meter gain filter configuration lm_gf bit in lreg10 this bit selects a gain factor of 1 or 16 for the level meter gain filter. level meter rectifier enable lm_rect bit in lreg10 this bit is used to enable or disable the level meter rectifier as required. level meter integrator work mode lm_once bit in greg16 this bit determines whether the integrator works once or continuously. offset register in the level meter dc_oft bit in lreg4 word dc offset in the coe-ram dc_oft = 0: the compensation value in the coe-ram is selected for the offset register; dc_oft = 1: the default compensation value of 0 is selected for the offset register. 45 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range 3.9.5 measurement via ac level meter 3.9.5.1 current measurement via vtac in order to measure current vi a the vtac pin, all feedback loops (impedance matching filters and trans hybrid balance filter) should be disabled. to simplify the formul as, the programmable receive and transmit gain (gtx, frx, grr and f rr) are disabled by corresponding registers (refer to ?3.3.2 programmable filters? on page 21 for details). based on this a factor k adac (gain of analog to digital in ac loop) can be defined: the transversal current i rms measured at the rslic: lm result: lm result = lm value / 32768 n samples: n samples = lm_cn k int: value of the shift factor k itac: value of the ac current to voltage converter for transversal voltage ( r sense is the sense resistance) 3.9.5.2 ac level meter operational state flow the operational state flow for the ac level meter is as the following: 1. the level meter is in the disable state (lm_en = 0), the result registers (greg17 & greg18) are cleared. 2. set the level meter count number (lm_cn[10:0]) in registers greg15 and greg16. 3. enable the level meter (lm_en =1) and it starts to accumulate the samples. when the preset count number is reached, the lm_ok bit is set and the accumulation result will be latched into the result registers simultaneous ly. if the result exceeds the preset threshold, the othre bit in lreg10 will be set. 4. if the lm_once bit is 0 (continuous mode), the level meter continues to measure the next samples right after one measurement is finished, the lm_ok bit is reset after 125 s. 5. if the lm_once bit is 1 (single mode), the level meter runs one time after the it is initiated and the lm_ok bit will not be reset until the lm_en bit is set to 0. 3.9.6 measurement via dc level meter 3.9.6.1 offset cu rrent measurement the current offset error is caused by the current sensor inside the rslic. the current offset can be measured by the dc level meter. the following settings are necessary to accomplish this measurement: ? the rslic is set to normal active mode (for mpi interface, lreg6: scan_en = 1, sm[2:0] = 000; for gci interface, downstream c/i channel: scan_en = 1, sm[2:0] = 000) and the loop is on-hook. in this condi tion, there should be no current present, but the current sensor incorrectly indicates a current flowing (current offset error). ? select vtdc and vl to the dc level meter separately (by setting bits lm_sel[3:0] in lreg9 to ?0000? and ?1001? respectively). ? the value in the offset register must be set to 0 (by clearing the word/dc offset in the coefficient ram). ? then the transversal and longitudinal offset currents ( i tdc,off-err and i ldc,off-err ) can be calculated. k itdc: value of the dc current to voltage converter for transversal current ( r sense is the sense resistance) k il: value of the current to voltage for longitudinal current k int: value of the shift factor k addc: gain of analog to digital conversion in the dc loop 3.9.6.2 leakage current measurement the leakage current tip/ring, l eakage current tip/gnd and leakage current ring/gnd can be measured by the dc level meter when the rslic is in on-hook mode. the following settings are necessary to accomplish the leakage current measurement: ? the rslic must be set to normal active mode when measuring the leakage current tip/ring. ? the rslic must be set to tip open mode when measuring the leakage current ring/gnd. ? the rslic must be set to ring open mode when measuring the leakage current tip/gnd. ? select vtdc to the dc level meter (lreg9: lm_sel[3:0]= 0000); ? i leakage can be calculated as shown below: k adac 1 = i rms lm result k adac k int n samples k itac 2 2 ------------------------------------------------------------------------------------------------ = k itac 8 r sense = v tdc off , err ? lm result k addc k int n samples ----------------------------------------------------------------- - = v ldc off , err ? lm result k addc k int n samples ----------------------------------------------------------------- - = i tdc off , err ? v tdc off , err ? k itdc -------------------------------- - = i ldc off , err ? v ldc off , err ? k il ------------------------- - = k itdc 2 5 -- - r sense = k il r sense = k addc 1 2 -- - = i leakage tipiend ? lm result 2 k addc k int n samples k itdc ---------------------------------------------------------------------------- - i tdc off , err ? i ldc off , err ? ? 2 --------------------------------------------------------- - ? = i leakage ringiend ? lm result 2 k addc k int n samples k itdc ---------------------------------------------------------------------------- - i tdc off , err ? i ldc off , err ? + 2 ---------------------------------------------------------- ? = i leakage tipiring ? lm result 2 k addc k int n samples k itdc ---------------------------------------------------------------------------- - i tdc off , err ? ? = 46 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range 3.9.6.3 loop resistance measurement the dc loop resistance can be det ermined by supplying a constant dc voltage ( v trdc ) to the tip/ring pair and measuring the dc loop current via the vtdc pin. the following steps are necessary to accomplish the loop resistance measurement: ? program a certain ring offset voltage (refer to ?3.4.1.1 internal ringing generation? on page 23 for details) and apply it to the tip/ring pair; ? set the rslic to normal active mode (for mpi interface, lreg6: scan_en = 1, sm[2:0] = 000; for gci interface, downstream c/i channel: scan_en = 1, sm[2:0] = 000). set the codec to ring pause mode (for both mpi and gci interfaces, lreg6: ring = 1, ring_en = 0). ? select vtdc as the level meter source (lm_src = 0; dc_src = 1; lm_sel[3:0] = 0000); ? the transversal current ( i trans ) can be determined by reading the level meter result registers (greg17 and greg18); ? based on the known constant output voltage v trdc and the mea- sured i trans current, the resistance can be calculated. it should be noted that the calculated resistance also includes the on board sense resistors. figure - 24 shows an example circuit for loop resistance measurement. in order to increase the accuracy of the result, either the current offset can be compensated or the measurement can be done differentially. the latter eliminates both the current and voltage offsets. to measure the loop resistance r loop differentially, follow the sequence below: ? program a certain ring offset voltage and apply it to the tip/ring pair via the rslic; ? set the rslic to normal active mode (for mpi interface, lreg6: scan_en = 1, sm[2:0] = 000; for gci interface, downstream c/i channel: scan_en = 1, sm[2:0] = 000). set the codec to ring pause mode (for both mpi and gci interfaces, lreg6: ring = 1, ring_en = 0). ? select vtdc as the level meter source (lm_src = 0; dc_src = 1; lm_sel[3:0] = 0000); ? read level meter result registers greg17 and greg18. ? reverse the voltage between tip and ring lines by setting the rev_pol bit in lreg19 to 1. ? read level meter result registers greg17 and greg18. figure - 25 describes the offset elimination by the differential measurement method. this differential measurement method eliminates both the current offset caused by the rslic current sensor and the voltage offset caused by the dc voltage output (ring offset voltage). the following calculation shows the elimination of both offsets. v offset: offset voltage caused by the dc voltage output; i offset: offset current caused by the rslic current sensor; 3.9.6.4 line resistance tip/gnd and ring/gnd the line resistance tip/gnd and ring/gnd can be measured by setting the ring and tip lines to high impedance respectively. when one line is set to high impedance, the other line is still active and is able to supply a known voltage. by measuri ng the dc transversal current, the line impedance can be determined. figure - 24 example for resistance measurement r loop v trdc i trans ----------------- v trdc lm result k addc k int n samples k itdc -------------------------------------------------------------------------- ?? ?? ? == rslic codec vtdc dcp dcn v trdc r sense i line r line line sense signal to be measured v trdc : dc voltage programmed by the coe-ram (word ringoffset) line card vl r prot r sense r prot figure - 25 differential resistance measurement i tip/ring v tip/ring di du i offset u offset offsets expected values measured values normal polarity reverse polarity i measure normal () v trdc v offset + r loop ---------------------------------- i offset + = i measure reverse () v ? trdc v offset + r loop ------------------------------------- i offset + = i measure normal () i measure reverse () ? 2 v trdc r loop ---------------------- - = r loop 2 v trdc i measure normal () i measure reverse () ? ------------------------------------------------------------------------ r line r sense r prot ++ == 47 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range because one line (tip or ring) is high impedance, there is only current flowing through the other line. this causes the calculated current to be half of the actual value. therefore in either ring open or tip open mode the calculated current must be multiplied by a factor of 2. v tgdc: dc voltage applied to tip/gnd v rgdc: dc voltage applied to ring/gnd. 3.9.6.5 capacitance measurement ? ramp generator the rslic-codec chipset integrates a ramp generator to help to measure the capacitance. the ra mp generator can generate required voltage ramps to feed to the ring and tip lines. figure - 26 shows the voltage ramp and the voltage levels at the ring and tip lines. the ramp generator is progr ammable by the coe-ram: ? slope is programmable from 20 to 2000 v/s by word rampslope; ? start voltage is programmable from -70 to 70 v by word ringoffset; ? end voltage is programmable from -70 to 70 v by word rampend. the following settings are nece ssary to generate a ramp signal: 1. set the codec operating mode to ramp (for both mpi and gci interfaces, lreg6: ramp = 1). 2. set the rslic operating mode to in ternal ring (for mpi interface, lreg6: scan_en = 1, sm[2:0] = 010; for gci interface, downstream c/i channel: scan_en = 1, sm[2:0] = 010). 3. select desired ramp start voltage, end voltage and slope (lreg5: rg = 1, constant parameters for the ramp are selected; lreg5: rg = 0, ramp param eters are programmed by the coefficient ram, refer to table - 23 on page 62 for details). r tip i gnd v tgdc lm result 2 k addc k int n samples k itdc -------------------------------------------------------------------------- ?? ?? ? = r ring i gnd v rgdc lm result 2 k addc k int n samples k itdc -------------------------------------------------------------------------- ?? ?? ? = figure - 26 capacitance measurement ring v dc,start ring tip v dc,end programmable voltage slope line current greg16: lm_en lreg21: lm_ok lreg21: ramp_ok int. period t ring,delay v bat / 2 v bat gnd rslic tip lreg8: ramp_en 48 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range 4. enable the ramp generator (lreg8: ramp_en = 1). once the ramp_en bit is set to 1, a ramp signal will start from the start voltage and increases its vo ltage following the programmed slope. when the voltage of the ramp signal finally reaches the programmed end voltage, the ramp_ok bit in lreg21 will be set to indicate that the ramp generation is finished. an interrupt will be generated simultaneously if the ramp mask bit ramp_m in lreg18 is 0. table - 18 lists the registers and coe-ram locations used for ramp generation. ? capacitance measurement the sequence of capacitance measurem ent is as the following (also refer to figure - 26 ): 1. configure the ramp generator (p rogram the ramp slope, start voltage and end voltage); 2. select the vtdc voltage to the dc level meter; 3. configure the level meter integrator (greg16: lm_once = 1); 4. enable the ramp generator (lreg8: ramp_en = 1); 5. after the current has settled, enable the level meter (greg16: lm_en = 1). (note: the ramp voltage starts at ringoffset and ramps up/down until rampend is reached. when the integration is finished, the result will be stored in registers greg17 and greg18). 6. read the result in greg17 and greg18. the actual current can be calculated as: i(t) = c measure du/dt where, du/dt is the ramp slope and i(t) is the current measured by the level meter. the capacitance then can be calculated as: to ensure measurement accuracy, the level meter integrator must be enabled after the current has settled to a constant value. the integration time is programmed by the lm_cn[ 10:0] bits in greg15 and greg16. 3.9.6.6 voltage measurement the dc level meter can measure the following voltages: ? external voltage tip/gnd (through io4 pin) ? external voltage ring/gnd (through io3 pin) ? external voltage tip/ring (through io4 -io3) ? ringing voltage (through io4 -io3) ? supply voltage vdd of the codec the two programmable io pins (io3 and io4) with analog input functionality can be used to measur e external voltages. if io3 and io4 pins are connected properly over a voltage divider to the ring and tip lines, the external voltage supplied to the lines can be measured on either io3 or io4 pin, or on io4- io3 (differential measurement). the lm_sel[3:0] bits in lreg9 select an external voltage to be measured. refer to table - 13 on page 40 for details. figure - 27 shows the connection and external resistors used for external voltage measurements at the ring and tip lines. the voltage measured on io3, io4 or io4-io3 is as follows (with a reference to vcm): table - 18 registers and coe-ram lo cations used for ramp generator parameter register bits/coe-ram words notes ramp parameters selection bit rg in lreg5 rg = 0: the ramp slope, start voltage and end voltage in the coe-ram are selected. rg = 1: the ramp slope, start voltage and end voltage in the rom are selected (default); ramp start voltage word ringoffset in the coe-ram programmable from -70 v to 70 v with 1% tolerance. the default value in the rom is 7 v. ramp slope word rampslope in the coe-ram programmable from 20 v/s to 2000 v/s with 1% tolerance. the default value in the rom is 300 v/s. ramp end voltage word rampend in the coe-ram programmable from -70 v to 70 v with 1% tolerance. the default value in the rom is 20 v. ramp mode selection bit ramp in lreg6 the ramp signal can only be generated in the ramp mode (ramp = 1). ramp generator enable bit ramp_en in lreg8 ramp_en = 0: the ramp generator is disabled; ramp_en = 1: the ramp generator is enabled. ramp over indication bit ramp_ok in lreg21 ramp_ok = 0: the ramp generation is in progress; ramp_ok = 1: the ramp generation is finished. mask bit for ramp_ok bit ramp_m in lreg18 ramp_m = 0: an interrupt will be generated when the ramp_ok bit changes from 0 to 1; ramp_m = 1: interrupts will not be generated when the ramp_ok bit changes. c measure it () du () dt () ? ------------------------ - lm result k addc k int n samples k itdc ---------------------------------------------------------------------------- - ?? ?? du dt ----- - ?? ?? ? == figure - 27 external voltage measurement principle rslic codec vtdc dcp dcn r sense r sense line card vl ac dc r1 r2 r3 r4 vcm vcm io4 io3 external voltage source v io 4 lm result k addc k int n samples ------------------------------------------------------- vcm + = 49 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range in figure - 27 , if r 1 = r 3 , r 2 = r 4 , the external voltage can be calculated as: when measuring the ringing volt age, the following steps are necessary: ? set the level meter integration time (lm_cn[10:0] bits in greg15 and greg16) to be an integer multiple of the period of measured ringing signal. ? clear the offset register (wor d dc offset in the coe-ram). ? measure the dc content with the rectifier disabled. ? read the result ( lm value ) from the result registers and write the following offset value to the offset register: ? repeat the measurement above should result in lm value to be zero. ? perform a new measurement with the rectifier enabled. the result is the rectified mean value of the measured signal and can be calculated as: ? from this result the peak value and the rms value can be calculated. the power supply of the codec (vdd) can be measured by selecting the vdd voltage to the dc level meter. when measuring the vdd voltage, an internal gain stage ( gain = 1/2) is used to divide the vdd voltage and provide a limited voltage to the level meter. the vdd is measured with a reference to vcm. 3.9.6.7 voltage offset measurement the filter, a/d conversion and decimation stages in the dc level meter may cause a voltage offset error. when selecting the vcm voltage as the source to the dc level meter, the voltage offset can be measured. once the offset value is determined, the offset error can be eliminated by writing an appropriate compensati on value to the offset register (word dc offset in the coe-ram). 3.9.6.8 ring trip operational amplifier offset measurement in external ringing mode, the sens ed ring current signal is fed to an operational amplifier integrated in the rslic. the amplifier will output a signal to the codec through the rtin pin for ring trip detection. but this amplifier may introduce an offset and affect the ring trip detection result. the offset can be measured by selecting the rtin as the source to the dc level meter. refer to ?3.4.2.1 ring trip detection in external ringing mode? on page 25 for details. v io 3 lm result k addc k int n samples ------------------------------------------------------- vcm + = v io 4 io 3 ? lm result k addc k int n samples ------------------------------------------------------- = v t ip i gnd r 1 r 2 + r 2 ---------------- v io 4 vcm ? () vcm + = v ring i gnd r 1 r 2 + r 2 ---------------- v io 3 vcm ? () vcm + = v t ip i ring r 1 r 2 + r 2 ---------------- v io 4 v io 3 ? () = offset lm value n samples k int ---------------------------------- - = v mean lm result k itdc r sense k addc k int n samples ---------------------------------------------------------- = v peak v mean 2 ------------------------------- - = v rms v peak 2 ----------- - lm result k itdc r sense k addc k int n samples 22 ----------------------------------------------------------------------------- - == vdd lm result k addc k int n samples ------------------------------------------------------- vcm + ?? ?? ?? 2 = 50 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 4interface the rslic-codec chipset provides two different types of digital interfaces to connect the codec to the digital network. one is a pcm interface combined with a serial microprocessor interface (pcm/mpi), the other is a general circuit interface (gci). the mpi /gci pin of the codec is used to select the interface. mpi /gci = 0: pcm/mpi interface is selected; mpi /gci = 1: gci interface is selected. 4.1 pcm/mpi interface in pcm/mpi mode, the voice data and control data are separate and transmitted via the pcm interface and mpi interface respectively. 4.1.1 mpi control interface in pcm/mpi mode, all the control information including internal registers configuring, coefficients programming and rslic controlling is transferred through the mpi control inte rface. this interface consists of four pins: cclk: serial control interface clock, up to 8.192 mhz cs : chip select pin. a low level on it enables the serial control interface ci: serial control data input pin, carrying the data from the master microprocessor to the codec. co: serial control data output pin, carrying the data from the codec to master microprocessor. all the data transmitted and received through the mpi interface is aligned in an 8-bit byte stream. the data transfer is synchronized to the cclk signal. the contents of ci is latched on the rising edges of cclk, while co changes on the falling edge of cclk. before finish executing a command followed by data bytes, t he device will not accept any new commands from ci. setting the cs pin to high will terminate the data transfer sequence. figure - 28 and figure - 29 show the read operation timing and write operation timi ng of the mpi interface. the cclk is the only reference for the ci and co pins. its duty and frequency may not necessarily be standard. figure - 28 mpi read operation timing cs cclk ci 76543210 command high "z" co 76543210 76543210 id data byte 1 high "z" figure - 29 mpi write operation timing cs cclk ci 76543210 command high "z" co 76543210 76543210 data byte 1 data byte 1 51 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 4.1.2 pcm interface in pcm/mpi mode, the pcm data (a/-law compressed code or linear code) is transferred through the pcm interface. the codec provides two transmit and two re ceive pcm highways for all four channels. the pcm interface consists of eight pins as shown below: fsc: frame synchronization clock bclk: pcm bit clock dx1: pcm transmit data highway 1 dr1: pcm receive data highway 1 tsx1 : pcm data transmit indicator 1, active low dx2: pcm transmit data highway 2 dr2: pcm receive data highway 2 tsx2 : pcm data transmit indicator 2, active low 4.1.2.1 pcm clock configuration the pcm interface is flexible with the data rate, clock slope and delay period programmable. the data rate can be the same as the bclk (single clock mode) or half of it (double clock mode). this is done by setting the dbl_clk bit in register greg3 to 0 and 1 respectively. the pcm data can be transmitted and received either on the rising edge of the bclk signal or on the falli ng edge of it. the pcm clock slope is selected by the tr_slope[1:0] bits in register greg3. refer to figure - 30 for details. the time slots for transmitting and receiving data can be offset from the fsc signal by 0 to 7 bclk period(s). the pcm_oft[2:0] bits in greg3 are used to set the offset period of the pcm timing. figure - 30 pcm clock slope select waveform bit 7 time slot 0 fsc bclk bclk transmit receive (single clock mode) (double clock mode) dbl_clk = 0 tr_slope[1:0] = 00 dbl_clk = 0 tr_slope[1:0] = 01 dbl_clk = 0 tr_slope[1:0] = 10 dbl_clk = 0 tr_slope[1:0] = 11 dbl_clk = 1 tr_slope[1:0] = 00 dbl_clk = 1 tr_slope[1:0] = 01 dbl_clk = 1 tr_slope[1:0] = 10 dbl_clk = 1 tr_slope[1:0] = 11 programmed by greg3: 52 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 4.1.2.2 time slot assignment the pcm data of each channel can be assigned to any time slot of the pcm highway. the number of the available time slots is determined by the bclk frequency. if the bclk frequency is f khz, the number of the time slots that can be used is the result of f (khz) divided by 64 khz. for example, if the frequency of bclk is 512 khz, then a total of eight time slots are availabl e. the codec accepts any bclk signals ranging from 256 khz to 8.192 mhz at increment of 64 khz. if the pcm data is a-law or -law compressed (8-bit), the voice data of one channel occupies one time slot. the tt[6:0] bits in lreg1 select the transmit time slot, while the rt[6:0] bits in lreg2 select the receive time slot. the ths bit in lreg1 selects the transmit highway (dx1 or dx2). the rhs bit in lreg2 selects the receive highway (dr1 or dr2). for linear pcm data, which is a 16- bit 2's complement (b13 to b0 are data bits, while b15 and b14 are the same as the sign bit b13), one time slot group consisting of two successive time slots are needed to contain the voice data of one channel. the tt[6:0] bits in lreg1 select the transmit time slot group. for exampl e, if the tt[6:0] bits are set to ?0000000?, it means that ts0 and ts1 are selected; if the tt[6:0] bits are set to ?0000001?, it means that ts2 and ts3 are selected. the rt[6:0] bits in lreg2 select the receive time slot group in the same way. 4.1.2.3 pcm highway selection the pcm data of each channel is sent out to the pcm highway on the selected edges of the bclk. the transmit highway (dx1 or dx2) is selected by the ths bit in lreg 1. the frame sync signal (fsc) identifies the beginning (time slot 0) of a transmit frame. the pcm data is transmitted serially to dx1 or dx2 with msb first. the pcm data from the master pr ocessor is received via the pcm highway on the selected edges of t he bclk. the receive highway (dr1 or dr2) is selected by the rhs bit in lreg2. the pcm data is received serially from dr1 or dr2 with msb first. the frame sync signal (fsc) identifies the beginning (time slot 0) of a receive frame. 4.2 gci interface the general circuit interface (gci) defines an industry-standard serial bus for interconnecting telecommunication ics for a broad range of applications ? typically isdn-based appl ications. the gci bus provides a symmetrical full-duplex communication link containing data, control/programming and status channel s. providing data, control and status information via a serial channel simplifies the line card layout and reduces the cost. the gci interface consists of tw o data lines and two clock lines as follows: du: data upstream carries data from the codec to the master processor dd: data downstream carries data from the master processor to the codec fsc: frame synchronization signal (8 khz) supplied to the codec dcl: data clock signal (2.048 mhz or 4.096 mhz) supplied to the codec the codec sends upstream dat a to the du pin and receives downstream data via the dd pin. a complete gci frame is sent upstream and received downstream every 125 s. the frame sync signal (fsc) identifies the beginning of the transmit and receive frames and all gci time slots are referenced to it. the internal circuit of the codec monitors the input dcl signal to determine which frequency (2.048 mhz or 4.096 mhz) is being used. the internal timing will be adjusted accordingly so that du and dd operate at 2.048 mhz rate. the codec allows both compressed and linear data format coding/ decoding. the l_code bit in greg3 selects the data format: l_code = 0: compressed code (default) l_code = 1: linear code 4.2.1 compressed gci mode in gci compressed mode, one gci frame consists of 8 gci time slots. in each gci time slot, the dat a upstream interface transmits four 8-bit bytes. they are: ? two voice data bytes from the a- law or -law compressor of two different channels, named channel a and channel b. the compressed voice data bytes for channel a and b are 8-bit wide: ? one monitor channel byte, contai ning the control data/coefficients from/to the master device for channel a and b; ? one c/i channel byte, which contai ns a 6-bit c/i sub-byte together with an mx bit and an mr bit. all real time signaling information is carried on the c/i sub-byte. the mx (monitor transmit) bit and mr (monitor receive) bit are used for handshaking functions for channel a and b. both mx and mr are active low. the transmit logic controls the trans mission of data onto the gci bus. the downstream data structure is the same as that of upstream. the data downstream interface logic cont rols the reception of data bytes from the gci bus. the two compressed voice data bytes of the gci time slot are transferred to the a-law or -law expansion logic circuit. the expanded data is passed through the receive path of the signal processor. the monitor channel an d c/i channel bytes are transferred to the gci control logic for process. figure - 31 shows the structure of the overall compressed gci frame. in gci compressed mode, two gci time slots are required to access all four channels of the codec. the gci time slot assignment is determined by s1 and s0 pins as shown in table - 19 . 4.2.2 linear gci mode in gci linear mode, one gci frame c onsists of eight gci time slots and each gci time slot consists of four 8-bit bytes. four of the eight gci time slots are used as the moni tor channel and c/i channel. they have a common data structure as follows: ? two don?t care bytes. ? one monitor channel byte, contai ning the control data/coefficients from/to the master device for channel a and b. ? one c/i channel byte, which contai ns a 6-bit c/i sub-byte together with an mx bit and an mr bit. all real time signaling information is carried on the c/i sub-byte. the mx (monitor transmit) bit and mr (monitor receive) bit are used for handshaking functions for channel a and b. both mx and mr bits are active low. the other four gci time slots ar e used to contain the linear voice data (a 16-bit 2?s complement number: b13 to b0 are data bits, while b15 and b14 are the same as the sign bit b13). each gci time slot consists of four bytes: two bytes for the 16-bit linear voice data of channel a, the other two bytes for the 16- bit linear data of channel b. the gci time slot assignment is determined by the s1 and s0 pins. when s0 and s1 are both low, the linear gci frame structure is as shown in figure - 32 on page 54 . in linear operation, for one chip of the four-channel codec occupies 53 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range four gci time slots (two for voice data and two for c/i and monitor channels), the remaining four gci time slots can be used by another chip if you were to tie their control busses together. hence, for an 8- timeslot gci bus, there are four ti me slot locations for one codec to select. see table - 20 on page 54 for details. figure - 31 compressed gci frame structure table - 19 time slot selection for compressed gci codec channel s1 = 0, s0 = 0 s1 =0, s0 = 1 s1 = 1, s0 = 0 s1 = 1, s0 = 1 time slot voice channel time slot voice channel time slot voice channel time slot voice channel 1 time slot 0 a time slot 2 a time slot 4 a time slot 6 a 2 time slot 0 b time slot 2 b time slot 4 b time slot 6 b 3 time slot 1 a time slot 3 a time slot 5 a time slot 7 a 4 time slot 1 b time slot 3 b time slot 5 b time slot 7 b ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 detail voice channel a voice channel b monitor channel c/i channel m r m x voice channel a voice channel b monitor channel c/i channel m r m x 125 s fsc dcl dd du du dd detail 54 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range figure - 32 linear gci frame structure table - 20 time slot selection for linear gci codec channel s1 = 0, s0 = 0 s1 =0, s0 = 1 time slot monitor and c/i channel time slot voice channel time slot monitor and c/i channel time slot voice channel 1 time slot 0 a time slot 2 a time slot 2 a time slot 4 a 2 time slot 0 b time slot 2 b time slot 2 b time slot 4 b 3 time slot 1 a time slot 3 a time slot 3 a time slot 5 a 4 time slot 1 b time slot 3 b time slot 3 b time slot 5 b codec channel s1 = 1, s0 = 0 s1 = 1, s0 = 1 time slot monitor and c/i channel time slot voice channel time slot monitor and c/i channel time slot voice channel 1 time slot 4 a time slot 6 a time slot 6 a time slot 0 a 2 time slot 4 b time slot 6 b time slot 6 b time slot 0 b 3 time slot 5 a time slot 7 a time slot 7 a time slot 1 a 4 time slot 5 b time slot 7 b time slot 7 b time slot 1 b ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 detail a unused unused monitor channel c/i channel m r m x unused unused monitor channel c/i channel m r m x 125 s fsc dcl dd du du dd detail a detail b du dd detail b 16-bit linear voice data for channel a 16-bit linear voice data for channel b 16-bit linear voice data for channel a 16-bit linear voice data for channel b ts0-1 for monitor and c/i ts2-3 for linear voice data 55 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 4.2.3 command/indication (c/i) channel the downstream and upstream comm and/indication (c/i) channels are continuously (every frame) carr ying i/o information to and from the codec. real-time signaling information for the two channels (a & b) are transferred via the six c/i bits. the two least significant bits of the c/ i bytes (mr and mx) are handshaking bits for the monitor channel. the codec transmits or receives t he c/i channel data with the most significant bit first. 4.2.3.1 downstream c/i channel byte the downstream c/i channel byte is used to control the operating mode of the rslic. this byte is defined as: this byte is shared by two channels (a & b) to transfer information. the c a and c b bits indicate whether the current c/i byte is for channel a or channel b respectively: c a = 1: the control information carrying by the scan_en and sm[2:0] bits is for channel a. c b = 1: the control information carrying by the scan_en and sm[2:0] bits is for channel b. the sm[2:0] bits are used to c onfigure the operating mode of the respective rslic. the scan_en bit in this byte determines whether the corresponding rslic will be accessed. refer to ?6.1.2 rslic operating modes? on page 89 for detailed information. by properly program the downstream c/i channel byte, users can configure the operating mode of every channel as required. 4.2.3.2 upstream c/i channel byte the upstream c/i channel byte quickly transfers the most time-critical information from the chipset to the master device. the definition of this byte is as follows: the six c/i bits in this byte is illustrated below: hooka: hook state of channel a hooka = 0: channel a is on-hook hooka = 1: channel a is off-hook hookb: hook state of channel b hookb = 0: channel b is on-hook hookb = 1: channel b is off-hook gndka: ground-key information of channel a gndka = 0: no longitudinal current is detected in channel a gndka = 1: longitudinal current is detected in channel a gndkb: ground-key information of channel b gndkb = 0: no longitudinal current is detected in channel b gndkb = 1: longitudinal current is detected in channel b int_cha: interrupt information of channel a int_chb: interrupt information of channel b the valid polarity of int_cha and int_chb depends on the int_pol bit in greg24: int_pol = 0: active low (default) int_pol = 1: active high downstream c/i channel byte msb lsb c a c b scan_en sm[2] sm[1] sm[0] mr mx upstream c/i channel byte msb lsb int_cha hooka gndka int_chb hookb gndkb mr mx 56 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 4.2.4 gci monitor transfer protocol 4.2.4.1 monitor channel operation in gci mode, upstream processors access the registers and ram of the chipset via the monitor channel. using two monitor control bits mr and mx per direction (the mr and mx bits are contained in the c/i channel bytes), data is trans ferred between the upstream and downstream devices in a complete handshake procedure. figure - 33 shows the monitor channel operating diagram. the transmission of the monito r channel is operated on a pseudo- asynchronous basis: ? data transfer (bits) on the bus is synchronized to fsc; ? data flow (bytes) are asyn chronously controlled by the handshake procedure. for example: data is placed ont o the dd monitor channel by the monitor transmitter of the master dev ice (dd mx bit is activated and set to 0). this data transfer will be r epeated within each frame (125 s rate) until it is acknowledged by the codec monitor receiver by setting the du mr bit to 0. because of t he handshaking protocol required for successful communication, the data transfer rate using the monitor channel is less than 8 kbit/s. 4.2.4.2 monitor handshake procedure the monitor channel works in three states: i. idle state: both the mr and mx bits are inactive (?1?) during two or more consecutive frames signals an idle state on the monitor channel or an end of message (eom); ii. sending state: the mx bit is activated ('0') by the monitor transmitter, together with a data by te (can be changed) on the monitor channel; iii. acknowledging: the mr bit is se t to active state ('0') by the monitor receiver, together with a data byte remaining in the monitor channel. a start of transmission is initiat ed by a monitor transmitter by sending out an active mx bit (?0?) together with the first byte of data to be transmitted in the monitor channel. this state remains until the addressed monitor receiver ack nowledges the receipt of data by sending out an active mr bit (?0?). the data transmission is repeated each 125 s frame (minimum is one r epetition). during this time the monitor transmitter keeps detecting the mr bit. flow control, means in the form of transmission delay, can only take place when the transmitter?s mx bit and the receiver?s mr bit are in active state. on the receiver side, since the m onitor data can be received at least twice (in two consecutive frames), a la st look function is able to check for data errors. if two different bytes are received the receiver will wait for the receipt of two identical successive bytes. on the transmitter side, a collision resolution mechanism is implemented to avoid two or more dev ices are trying to send data at the same time. the mechanism is realized by looking for the inactive (?1?) phase of the mx bit and making a per bit collision check on the transmitted monitor data (check whet her transmitted ?1?s are on the du/ dd line. the du/dd line are open drain). any abort leads to a reset of the codec command stack, and the device is ready to receive new commands. to obtain a maximum speed data tran sfer, the transmitter anticipates the falling edge of the receivers acknowledgment. due to the inherent programming structure, duplex operation is not possible. it is not allowed to send any data to the codec while transmission is active. note that each byte on the monitor channel must be sent twice at least according to the gc i monitor handshake procedure. refer to figure - 34 and figure - 35 for details about monitor handshake procedure. figure - 33 monitor channel operation monitor transmitter monitor receiver monitor receiver monitor transmitter master device codec mx mx mx mx mr mr mr mr dd du 57 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range figure - 34 state diagram of the monitor transmitter idle mx = 1 wait mx = 1 abort mx = 1 1st byte mx = 0 eom mx = 1 nth byte ack mx = 1 wait for ack mx = 0 mr or mxr mxr mr and mxr mr and mxr mr and rqt mr and rqt mr mr mr and rqt mr mr and rqt mr mr and rqt cls/abt any state initial state mr: mr bit received on dd line mx: mx bit calculated and expected on du line mxr: mx bit sampled on du line cls: collision within the monitor data byte on du line rqt: request for transmission from internal source abt: abort request/indication 58 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range by implementing proper register /ram commands through the gci monitor channel, users can flexibly control the rslic-codec chipset. the format and the addressing method of the register/ram in both gci mode and mpi mode are similar. refer to ?5.2 register/ram commands? on page 59 for details. 4.3 analog pots interface the interface between an anal og plain old telephone service (pots) and a rslic is shown in figure - 49 on page 104 . the rslic connects to the pots interface through the tip and ring pins. over voltage and over current protectors connect to the tip and ring pins directly. only two external resistors are needed to connect tis to tip and connect ris to ring respectively, no other components are required in the pots interface. 4.4 rslic and codec interface as figure - 49 shows, the rslic can be connected directly to the codec. the rslic can work in different modes that are determined by the codec through the slic mode control pins csn and m1 to m3. refer to ?6 operational description? on page 87 for details. figure - 35 state diagram of the monitor receiver idle mr = 1 nth byte rec mr = 1 wait for ll mr = 0 1st byte rec mr = 0 abort mr = 1 byte valid mr = 0 new byte mr = 1 mx mx and ll mx mx mx mx and ll mx mx and ll wait for ll mr = 0 initial state mx mx mx and ll mx and ll mx and ll mx mx any state abt mr: mr bit calculated and transmitted on du line mx: mx bit received data downstream (dd line) ll: last look of monitor byte received on dd line abt: abort indication to internal source 59 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 5 programming 5.1 overview programming the chipset is realiz ed via the serial microprocessor interface (mpi mode) or gci moni tor channel (gci mode). in mpi mode, the command or data is transferred via the ci/co pin. in gci mode, the command or data is transferred via the dd/du pin. 5.1.1 mpi programming 5.1.1.1 broadcast mode for mpi programming a broadcast mode is provided for mpi write-operation (not allowed for read-operation). each channel has its own channel enable bit (ch_en[0] to ch_en[3] in greg4 for channel 1 to channel 4, respectively) to allow individual channel programming. if two or more ch_en bits are set to 1 (enabl e), the corresponding channels are enabled and can receive the progra mming information simultaneously. therefore, a broadcast mode can be im plemented by simply enabling all of the channels in the device. the broadcast mode is very useful when initializing a large system, because the registers and ram locations of four channels can be configured by one operation. 5.1.1.2 identification code for mpi programming in mpi mode, an identification code is used to distinguish the codec from other devices in the system. in read operations, before outputting other data bytes, the codec will first output an identification code of 81h indicating that the fo llowing data is from the codec. 5.1.2 gci programming 5.1.2.1 program start by te for gci programming in gci mode, the codec exchanges status and control information with the master processor through the monitor channel. the messages transferred in the monitor channel have different data structures. since one monitor channel is shared by two voice data channels (channel a and channel b) to transfer status or c ontrol information, a program start (ps) byte is necessary to indicate the source (upstream) channel or the destination (downstream) channel dur ing data transferring. for a complete gci command operation, messages transferred via the monitor channel always start with a ps byte as follows: where, the a /b bit is used to identify the two channels: a /b = 0: 81h. channel a is the s ource (upstream) or destination (downstream). a /b = 1: 91h. channel b is the s ource (upstream) or destination (downstream). the program start byte will be followed by a register command (global/local register command) or a ram command (fsk-ram or coe- ram command). for global register commands, the a/b bit in the ps byte is ignored. 5.1.2.2 identification comm and for gci programming in order to distinguish different devices unambiguously by software, a two byte identification command of 8000h is defined for analog line gci devices: each device will respond with its specific identification code. for the idt82v1074, this two-byte ident ification code will be 8082h. 5.2 register/ram commands 5.2.1 register/ram command format for both mpi and gci modes, the command format is as the following: r /w: read/write command bit b7 = 0: read command b7 = 1: write command ct: command type b6 b5 = 00: local register command b6 b5 = 01: global register command b6 b5 = 10: fsk-ram command (one word operation) b6 b5 = 11: coe-ram command (eight words operation) address: b[4:0] specify the register (s) or the location(s) of ram to be addressed. 5.2.2 addressing the local registers in both mpi and gci modes, the loca l registers are used to configure each individual channel. up to 32 loca l registers are provided for each channel. the local registers are accessed by corresponding local commands. ?mpi mode in mpi mode, when addressing a local register, the channel enable register (greg5) must be first set to specify one or more channels to be addressed. for example, if the ch_en[0] bit in greg4 is set to 1, the local register(s) of channel 1 will be addressed. the ch_en[1] to ch_en[3] bits enable/disable the lo cal registers of channel 2 to channel 4, respectively, in the same way. in mpi mode, the codec provides an automatic countdown mechanism for addressing the local r egisters. when executing a local command, the codec will automatic ally count down from the address specified in b[4:0] to the address of 0. for example, if b[4:0] = 00001, the local register with the address of ?0 0001' will be accessed first, then the address will be counted down to ?00000? automatically and the corresponding local register will be accessed. since the address is b7 b6 b5 b4 b3 b2 b1 b0 100 a /b 0 0 0 1 1 0000 0 00 0 0000 0 00 1 0000 0 00 1 0000 0 10 b7 b6 b5 b4 b3 b2 b1 b0 r /w ct address 60 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range '00000' now, the codec will stop counting down and the addressing operation is finished. the number of the local register s addressed by a local command is b[4:0]+1. hence, up to 32(d) loca l registers can be addressed by one local command. to apply a write local command, total b[4:0]+1 bytes of data should follow to ensure proper operation. see table - 21 for details. in mpi mode, when the cs pin is pulled low, the codec treats the first byte present on the ci pin as command and the following byte(s) as data. to execute other commands, the cs pin must be changed from low to high to finish the previous command and then be changed from high to low to start the next command. the automatic count-down pr ocedure can be stopped by the cs pin at any time. if the cs pin changes from low to high during a addressing process, the operation for current local register and the rest local registers will be abort ed. but the operations accomplished before the cs pin goes high will hav e already been executed. to complete an automatic countdown procedure, the cs pin must remain low for more than on e data byte period after the last data byte is transmitted. refer to ?5.4.1.1 example of programming the local registers via mpi? on page 83 for more information. ?gci mode in gci mode, the b4 bit in the program start byte, together with the location of the time slot (determined by the s0 and s1 pin), specifies the local registers to be addressed. in gci mode, the codec provides a consecutive adjacent addressing method for reading and writi ng local registers. according to the value of b[1:0] specified in the local command, there will be one to four adjacent local registers to be addressed automatically with the highest order one first. for example, if the address bits b[4:0] are set to 'xxx11' in a local command, the codec will count down from the address 'xxx11' to the address 'xxx 00' automatically. the number of local registers to be addressed by one local command is b[1:0]+1. therefore, up to four local regi sters can be addressed by one local command in gci mode. refer to table - 22 for details. in gci mode, the procedure of t he consecutive adjacent addressing can not be stopped once a command is initiated. for a write operation, the number of the data bytes that follow the command byte must be the same as the number of the registers to be written. refer to ?5.4.2.1 example of program ming the local registers via gci? on page 85 for details. 5.2.3 addressing the global registers in both mpi and gci modes, the global registers are used to configure all four channels. the code c provides 32 global registers for all channels. the global registers are accessed by the corresponding global commands. ?mpi mode in mpi mode, the global register s are shared by all four channels, and there is no need to specify a channel or channels before addressing global registers. except for this, t he global registers are addressed in a similar manner as the local registers. see ?5.4.1.2 example of programming the global registers via mpi? on page 84 for details. ?gci mode in gci mode, the global command can be transferred during any of the gci time slots and all four channel wi ll receive it. except for this, the global registers are addressed in a si milar manner as the local registers. see ?5.4.2.2 example of programming the global registers via gci? on page 85 for details. 5.2.4 addressing the fsk-ram when sending a caller id message via fsk signal, the message table - 21 local register addressing in mpi mode address specified in a local command in/out data bytes address of the local registers to be accessed b[4:0] = 11111 32 bytes from ?11111? to ?00000? b[4:0] = 11110 31 bytes from ?11110? to ?00000? b[4:0] = 11101 30 bytes from ?11101? to ?00000? ... ... ... b[4:0] = 11000 25 bytes from ?11000? to ?00000? b[4:0] = 10111 24 bytes from ?10111? to ?00000? b[4:0] = 10110 23 bytes from ?10110? to ?00000? b[4:0] = 10101 22 bytes from ?10101? to ?00000? ... ... ... b[4:0] = 10000 17 bytes from ?10000? to ?00000? b[4:0] = 01111 16 bytes from ?01111? to ?00 000? b[4:0] = 01110 15 bytes from ?01110? to ?00000? b[4:0] = 01101 14 bytes from ?01101? to ?00000? ... ... ... b[4:0] = 01000 9 bytes from ?01000? to ?00000? b[4:0] = 00111 8 bytes from ?00111? to ?00000? b[4:0] = 00110 7 bytes from ?00110? to ?00000? b[4:0] = 00101 6 bytes from ?00101? to ?00000? ... ... ... b[4:0] = 00000 1 byte ?00000? table - 22 local register addressing in gci mode address specified in a local command in/out data bytes address of the local registers to be accessed b[4:0] = xxx11 byte 1 xxx11 byte 2 xxx10 byte 3 xxx01 byte 4 xxx00 b[4:0] = xxx10 byte 1 xxx10 byte 2 xxx01 byte 3 xxx00 b[4:0] = xxx01 byte 1 xxx01 byte 2 xxx00 b[4:0] = xxx00 byte 1 xxx00 61 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range data is stored in the fsk-ram that is shared by all four channels. the fsk-ram consists of 32 words, 16 bi ts (two bytes) per word. they are addressed by the fsk-ram commands. the b[4:0] bits in a fsk-ram command specify a location in the fsk-ram to be accessed. in both mpi and gci modes, when addressing a fsk-ram word, 16 bits wi ll be written to or read out from this word with msb first. ?mpi mode in mpi mode, the fsk-ram is addres sed in a similar manner as the local registers except the data is twice as long. when executing a fsk- ram command, the codec automat ically counts down from the address specified in the command (b[4:0]) to the address of '00000', resulting in total b[4:0]+1 words of fsk-ram being addressed. as the data written to or read out from t he fsk-ram is 16-bit (two-byte) wide, total (b[4:0]+1) ? 2 bytes of data will follow a fsk-ram command. refer to ?5.4.1.4 example of programming the fsk-ram via mpi? on page 84 for more information. ?gci mode in gci mode, the fsk-ram is addres sed in a similar manner as the local registers except the data is twice as long (the data for the fsk- ram is 16-bit wide while the data for lo cal registers is 8-bit wide). refer to ?5.4.2.4 example of programming the fsk-ram via gci? on page 86 for more information. 5.2.5 addressing the coe-ram the coe-ram (coefficient ram) c onsists of 12 blocks per channel, and each block consists of 8 words. so, there are total 96 words per channel. the coefficient ram mapping is shown in table - 23. each word in coe-ram is 14-bit wide. to write a coe-ram word, 16 bits (or two 8-bit bytes) are needed to fill one word with msb first , but the first two bits (msb) will be i gnored. when being read, each coe-ram word will output 16 bits with msb first, but the first two bits are meaningless. ?mpi mode in mpi mode, the coe-ram commands always follow the channel enable command that specifies which channel(s) to be accessed. the address (b[4:0]) in the coe-ram commands indicates which block of the coe-ram for the s pecified channel(s) will be addressed. the codec automatically counts down from the highest address to the lowest address of the specified blo ck. so one block (consists of eight words) can be addressed by one coe-ram command. in mpi mode, the procedure of reading/writing words from/to the coe-ram can be stopped by the cs pin at any time. when the cs pin changes from low to high, the operation on the current word and the next adjacent words will be aborted. but the operations that are accomplished before the cs pin goes high have been executed. see ?5.4.1.3 example of programmi ng the coefficient-ram via mpi? on page 84 for detailed information. ?gci mode in gci mode, both the location of time slot (determined by s1 and s0 pin) and the b4 bit in program start byte specify a channel of which the coe-ram will be addressed. the addr ess (b[4:0]) in the coe-ram command locates a block of the coe-ram. when executing a coe- ram command, all eight words in the block will be read/written automatically, with the highest order word first. in gci mode, the procedure of t he consecutive adjacent addressing can not be stopped once a coe-ram command is initiated. see ?5.4.2.3 example of programmi ng the coefficient-ram via gci? on page 85 for details. 62 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range table - 23 coefficient ram mapping word 7 word 6 word 5 word 4 word 3 word 2 word 1 word 0 offset/ address notes dc offset (default value: 0) reserved impedance matching filter (imf) coefficient (default: the imf is disabled) 00h block 0 reserved transhybrid balance filter (ecf) coefficient (default: the ecf is disabled) 01h block 1 gain for impedance scaling (gis) (default value: 0) reserved should be 2000h when using the dual tone genera- tors. (default: 0000h) (1) notes: 1. the default value of this word is 0000h. when using the dual tone generators, users should write 2000h (i.e. high byte: 20h, low byte: 00h) to this word to ensure proper operation. tg2freq (default: 1447 hz) tg2amp (default: 0.94 v) tg1freq (default: 852 hz) tg1amp (default: 0.94 v) 02h block 2 digital gain in transmit path (gtx) (default: 0 db) coefficient for frequency response correction in transmit path (frx) (default: the frx is disabled) 03h block 3 digital gain in receive path (grx) (default: 0 db) coefficient for frequency response correction in receive path (frr) (default: the frr is disabled) 04h block 4 reserved rampend (default: 20 v) rampslope (default:300v/s) ringoffset (default: 7 v) ringfreq (default: 30 hz) ringamp (default: 40 v) 05h block 5 dc feeding coefficient 06h block 6 reserved hkhyst (default: 2 ma) rtthld_ac (default: 5 ma) rtthld_dc (default: 5 ma) reserved hkthld (default: 7 ma) 07h block 7 utd integrator coefficient utd bandstop filter coefficient (2) 2. when the gains in the transmit and receive paths are 0 db, the default parameters of the utd filters are as follows: bandpass filter: center frequency is 2100 hz and bandwidth is 60 hz. bandstop filter: center frequency is 2100 hz and bandwidth is 230 hz. utd bandpass filter coefficient (2) 08h block 8 reserved utdthld_floor (default: ? 18 dbm) utdthld_ceiling (default: ? 6 dbm) reserved utd integrator coefficient 09h block 9 lm notch filter coefficient (3) 3. when the gains in the transmit and receive paths are 0 db, the default parameters of the level meter filter are as follows: bandpass/notch filter: center frequency is 1014 hz and quality factor (q) is 5. reserved 0ah block 10 lm bandpass filter coefficient (3) reserved 0bh block 11 63 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 5.3 registers description 5.3.1 registers overview table - 24 global registers mapping name function description register byte read command write command default value b7 b6 b5 b4 b3 b2 b1 b0 greg1 pll power down pll_pd reserved 20h a0h 00h greg2 reserved for future use reserved - - - greg3 pcm configuration l_code a/ dbl_clk tr_slope[1:0] pcm_oft[2:0] 22h a2h 40h greg4 mclk selection and channel enable ch_en[3:0] mclk_sel[3:0] 23h a3h 02h greg5 hardware/software reset and version information hw_rst reserved sw_rst reserved rch_sel[3:0] 24h a4h 00h greg6 loopback control reserved alb_64k alb_8k alb_di reserved dlb_64k dlb_8k dlb_di 25h a5h 00h greg7 three-party conference control reserved conf_en confx_en conf_cs[1:0] 26h a6h 00h greg8 gain of three-party conference g_conf[7:0] 27h a7h 00h greg9 transmit highway and time slot selection for part b ths_b tt_b[6:0] 28h a8h 00h greg10 receive highway and time slot selection for part b rhs_b rt_b[6:0] 29h a9h 00h greg11 transmit highway and time slot selection for part c ths_c tt_c[6:0] 2ah aah 00h greg12 receive highway and time slot selection for part c rhs_c rt_c[6:0] 2bh abh 00h greg13 transmit highway and time slot selection for part d ths_d tt_d[6:0] 2ch ach 00h greg14 receive highway and time slot selection for part d rhs_d rt_d[6:0] 2dh adh 00h greg15 level meter configuration 1 lm_cn[7:0] 2eh aeh 00h greg16 level meter configuration 2 lm_once lm_en lm_cs[1:0] reserved lm_cn[10:8] 2fh afh 00h greg17 level meter result (low) lmrl[7:0] 30h - 00h greg18 level meter result (high) lmrh[7:0] 31h - 00h greg19 fsk flag length fsk_fl[7:0] 32h b2h 00h greg20 fsk data length fsk_dl[7:0] 33h b3h 00h greg21 fsk seizure length fsk_sl[7:0] 34h b4h 00h greg22 fsk mark length fsk_ml[7:0] 35h b5h 00h greg23 fsk control reserved fsk_cs[1:0] fsk_en fsk_bs fsk_mas fsk_ts 36h b6h 00h greg24 interrupt polarity reserved int_pol reserved 37h b7h 00h greg25 reserved for future use reserved - - - greg26 off-hook, ground-key status and interrupt clear gk[3] hk[3] gk[2] hk[2] gk[1] hk[1] gk[0] hk[0] 39h b9h 00h 64 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range table - 25 local registers mapping name function description register byte read command write command default value b7 b6 b5 b4 b3 b2 b1 b0 lreg1 transmit highway and time slot selection ths tt[6:0] 00h 80h 00h for ch1 01h for ch2 02h for ch3 03h for ch4 lreg2 receive highway and time slot selection rhs rt[6:0] 01h 81h 00h for ch1 01h for ch2 02h for ch3 03h for ch4 lreg3 loopback control reserved dlb_2m dlb_pcm reserved alb_1mdc alb_2m alb_pcm cutoff 02h 82h 00h lreg4 coefficient selection frr grx frx gtx tg ecf imf dc_oft 03h 83h ffh lreg5 coefficient selection v90 hpf lm_b lm_n utd signaling dc_feed rg 04h 84h bfh lreg6 codec and rslic mode control p_down standby active ramp scan_en sm[2:0] 05h 85h 80h lreg7 analog gain selection, ac/ dc ring trip selection, ring generator and tone generators enable reserved im_629 ring rt_sel ring_en tg2_en tg1_en 06h 86h 00h lreg8 ramp generator enable, level meter path selection and notch/bandpass filter characteristic configuration, utd source selection and utd enable ramp_en reserved lm_notch lm_filt lm_src dc_src utd_src utd_en 07h 87h 00h lreg9 level meter source and shift factor selection k[3:0] lm_sel[3:0] 08h 88h 00h lreg10 level meter threshold, rectifier on/off, gain factor othre lm_gf lm_rect reserved lm_th[2:0] 09h 89h 00h lreg11 debounce filter db[3:0] db_io[3:0] 0ah 8ah 00h lreg12 pcm data low byte pcm[7:0] 0bh - 00h lreg13 pcm data high byte pcm[15:8] 0ch - 00h lreg14 utd rtime utd_rt[7:0] 0dh 8dh 13h lreg15 utd rbktime utd_rbk[7:0] 0eh 8eh 19h lreg16 utd etime utd_et[7:0] 0fh 8fh 40h lreg17 utd ebrktime utd_ebrk[7:0] 10h 90h 64h lreg18 interrupt mask reserved gk_m hk_m otmp_m ramp_m gkp_m 11h 91h 1fh lreg19 io interrupt mask, polarity reverse, external ringing sync enable reserved rev_pol sync_en io_m[3:0] 12h 92h 0fh lreg20 io pin direction select and io data io_c[3:0] io[3:0] 13h 93h 00h lreg21 interrupt source and dc feeding characteristic indication feed_i feed_v feed_r lm_ok utd_ok otmp ramp_ok gk_pol 14h - 01h 65 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range in the following global registers and local registers lists, it should be noted that: 1. r /w = 0, read command. r /w = 1, write command. 2. the reserved bit(s) in the register must be filled in ?0? in write operation and will be ignored in read operation. 3. the global or local registers described below are available for both mpi and gci modes except for those with special stateme nt. 5.3.2 global registers list greg1: pll power down, read/write (20h/a0h) pll_pd power down the internal pll block (refer to ?6.2 pll power down? on page 90 for details). pll_pd = 0: the internal pll block is powered up (default); pll_pd = 1: the internal pll block is powered down. other bits in this register are reserved for future use. greg2: reserved. this register is reserved for future use. greg3: pcm configuration, read/write (22h/a2h) l_code voice data code (8-bit, a/-law compre ssed code or 16-bit linear code) selection l_code = 0: compressed code is selected (default); l_code = 1: linear code is selected. a/ select the pcm law a/ = 0: -law is selected; a/ = 1: a-law is selected (default). dbl_clk clock mode (single or double) selection. this bit is used for mpi mode only . dbl_clk = 0: single clock is selected (default); dbl_clk = 1: double clock is selected. tr_slope[1:0] transmit and receive slope selection. the tr_slope[1:0] bits ar e used for mpi mode only . tr_slope[1:0]=00: transmits data on the rising edges of bclk , receives data on the falling edges of bclk (default); tr_slope[1:0]=01: transmits data on the rising edges of bclk, receives data on the rising edges of bclk; tr_slope[1:0]=10: transmits data on the falling edges of bclk, receives data on the falling edges of bclk; tr_slope[1:0]=11: transmits data on the falling edges of bclk, receives data on the rising edges of bclk; pcm_oft[2:0] pcm timing offset selection. t he pcm transmit/receive time slot can be of fset from fsc by 0 to 7 bclk periods. the pcm_oft[2:0] bits are used for mpi mode only . pcm_oft[2:0]=000: offset from fsc by 0 bclk period (default); pcm_oft[2:0]=001: offset from fsc by 1 bclk period; pcm_oft[2:0]=010: offset from fsc by 2 bclk periods; pcm_oft[2:0]=011: offset from fsc by 3 bclk periods; pcm_oft[2:0]=100: offset from fsc by 4 bclk periods; pcm_oft[2:0]=101: offset from fsc by 5 bclk periods; pcm_oft[2:0]=110: offset from fsc by 6 bclk periods; pcm_oft[2:0]=111: offset from fsc by 7 bclk periods. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0100000 i/o data pll_pd reserved b7 b6 b5 b4 b3 b2 b1 b0 command r /w0100010 i/o data l_code a/ dbl_clk tr_slope[1:0] pcm_oft[2:0] 66 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range greg4: master clock selection and channe l program enable, read/write (23h/a3h) ch_en[3:0] channel programming enable. in mpi mode, the channel programming enable command is used to specify the channel(s) to which the subsequent local command or co e-ram command will be applied. the ch_en[3:0] bits enable channel 4 to channel 1 for programming, respectively. the ch_en[3:0] bits are used for mpi mode only. ch_en[3] = 0: disabled, channel 4 can not receiv e local commands and coe-ram commands (default); ch_en[3] = 1: enabled, channel 4 can rece ive local commands and coe-ram commands; ch_en[2] = 0: disabled, channel 3 can not receiv e local commands and coe-ram commands (default); ch_en[2] = 1: enabled, channel 3 can rece ive local commands and coe-ram commands; ch_en[1] = 0: disabled, channel 2 can not receiv e local commands and coe-ram commands (default); ch_en[1] = 1: enabled, channel 2 can rece ive local commands and coe-ram commands; ch_en[0] = 0: disabled, channel 1 can not receiv e local commands and coe-ram commands (default); ch_en[0] = 1: enabled, channel 1 can rece ive local commands and coe-ram commands; mclk_sel[3:0] select the frequency of the master clock. in mp i mode, there are nine frequencies can be selected as the master clock. the mclk_sel[3:0] bits ar e used for mpi mode only. (in gci mode, the frequency of the master clock is either 2.048 mhz or 4.096 mh z, the same as the frequency of data clock (dcl). the internal circuit of the codec monitors the dcl input to determine which frequency is being used.) mclk_sel[3:0] = 0000: 8.192 mhz mclk_sel[3:0] = 0001: 4.096 mhz mclk_sel[3:0] = 0010: 2.048 mhz (default) mclk_sel[3:0] = 0110: 1.536 mhz mclk_sel[3:0] = 1110: 1.544 mhz mclk_sel[3:0] = 0101: 3.072 mhz mclk_sel[3:0] = 1101: 3.088 mhz mclk_sel[3:0] = 0100: 6.144 mhz mclk_sel[3:0] = 1100: 6.176 mhz greg5: hardware and software reset, wr ite (a4h); version number, read (24h) when write this register, a hardware or a softw are reset will be applied as described below: hw_rst hardware reset of the codec. the action of this hardware reset is equivalent to pulling the reset pin of the codec low. hw_rst = 0: no hardware reset signal will be generated (default); hw_rst = 1: a hardware rese t signal will be generated. sw_rst software reset of the codec. this software reset operati on resets those local registers specified by the rch_sel[3:0] bits, but the coe-ram is not affected. sw_rst = 0: no software reset signal will be generated (default); sw_rst = 1: a software reset signal will be generated. if the sw _rst bit is set to 1, those local registers specified by the rch_sel[3:0] bits will be reset, but other loca l registers and all the global registers as well as the coe-ram will not be affected. rch_sel[3:0] select channel(s) for software reset. the rch_sel[3:0] bits select the local registers of channel 4 to channel 1, respectively, to be reset. rch_sel[3] = 0: the local registers of channel 4 will not be reset after executing a software reset command (default)); rch_sel[3] = 1: the local registers of channel 4 wi ll be reset after executing a software reset command; b7 b6 b5 b4 b3 b2 b1 b0 command r /w0100011 i/o data ch_en[3:0] mclk_sel[3:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0100100 i/o data hw_rst reserved sw_rst reserved rch_sel[3 ] rch_sel[2] rch_sel[1] rch_sel[0] 67 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range rch_sel[2] = 0: the local registers of channel 3 will not be reset after execut ing a software reset command (default)); rch_sel[2] = 1: the local registers of channel 3 wi ll be reset after executing a software reset command; rch_sel[1] = 0: the local registers of channel 2 will not be reset after executing a software reset command (default); rch_sel[1] = 1: the local registers of channel 2 wi ll be reset after executing a software reset command; rch_sel[0] = 0: the local registers of channel 1 will not be reset after executing a software reset command (default); rch_sel[0] = 1: the local registers of channel 1 wi ll be reset after executing a software reset command; when read this register, the codec ve rsion number of 5ah will be read out. greg6: test loopback cont rol, read/write (25h/a5h) this register is used to enable the analog and digital loopbacks for testing. alb_64k analog loopback via 64 khz alb_64k = 0: alb_64k loopback is disabled (normal operation) (default); alb_64k = 1: alb_64k loopback is enabled. alb_8k analog loopback via 8 khz alb_8k = 0: alb_8k loopback is di sabled (normal operation) (default); alb_8k = 1: alb_8k loopback is enabled. alb_di analog loopback via dx to dr ( this loopback is available for mpi mode only ) alb_di = 0: alb_di loopback is dis abled (normal operation) (default); alb_di = 1: alb_di loopback is enabled. dlb_64k digital loopback via 64 khz dlb_64k = 0: dlb_64k loopback is dis abled (normal operation) (default); dlb_64k = 1: dlb_64k loopback is enabled. dlb_8k digital loopback via 8 khz dlb_8k = 0: dlb_8k loopback is dis abled (normal operation) (default); dlb_8k = 1: dlb_8k loopback is enabled. dlb_di digital loopback via dr to dx ( this loopback is available for mpi mode only ) dlb_di = 0: dlb_di loopback is di sabled (normal operation) (default); dlb_di = 1: dlb_di loopback is enabled. greg7: three-party conference conf iguration, read/write (26h/a6h) conf_en enable internal three-party conference conf_en = 0: internal confer ence is disabled (default); conf_en = 1: internal conference is enabled. confx_en enable external three-party conference confx_en = 0: external conf erence is disabled (default); confx_en = 1: external conference is enabled. conf_cs[1:0] select a channel for three-party conference conf_cs[1:0] = 00: channel 1 is selected (default); b7 b6 b5 b4 b3 b2 b1 b0 command r /w0100101 i/o data reserved alb_64k alb_8k alb_di reserved dlb_64k dlb_8k dlb_di b7 b6 b5 b4 b3 b2 b1 b0 command r /w0100110 i/o data reserved conf_en confx_en conf_cs[1:0] 68 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range conf_cs[1:0] = 01: channel 2 is selected; conf_cs[1:0] = 10: channel 3 is selected; conf_cs[1:0] = 11: channel 4 is selected. greg8: three-party conference gain setting, read/write (27h/a7h) g_conf[7:0] gain of three-party conference. t he gain is calculated by the following formula: gain = g_conf[7:0] / 256 the default value of g_cong[7:0] bits is 0(d). greg9: transmit time slot and highway selection for pa rt b in three-party confer ence, read/write (28h/a8h) ths_b transmit pcm highway selection for part b in three-party conference ths_b = 0: transmit pcm highway one (dx1) is selected (default); ths_b = 1: transmit pcm highway two (dx2) is selected. tt_b[6:0] transmit time slot selection for part b in three-party conference. the valid value of the tt_b[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of tt_b[6:0] is 0(d). greg10: receive time slot and highway selection for pa rt b in three party confer ence, read/write (29h/a9h) rhs_b receive pcm highway selection for part b in three-party conference rhs_b = 0: receive pcm highway one (dr1) is selected (default); rhs_b = 1: receive pcm highway two (dr2) is selected. rt_b[6:0] receive pcm time slot selecti on for part b in three-party conference. the valid value of the rt_b[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of rt_b[6:0] is 0(d). greg11: transmit time slot and highway selection for part c in three-party conf erence, read/write (2ah/aah) ths_c transmit pcm highway selection for part c in three-party conference ths_c = 0: transmit pcm highway one (dx1) is selected (default); ths_c = 1: transmit pcm highway two (dx2) is selected. tt_c[6:0] transmit time slot selection for part c in three-party conference. the valid value of the tt_c[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of tt_c[6:0] is 0(d). b7 b6 b5 b4 b3 b2 b1 b0 command r /w0100111 i/o data g_conf[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101000 i/o data ths_b tt_b[6:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101001 i/o data rhs_b rt_b[6:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101010 i/o data ths_c tt_c[6:0] 69 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range greg12: receive time slot and highway selection for pa rt c in three-party confer ence, read/write (2bh/abh) rhs_c receive pcm highway selection for part c in three-party conference rhs_c = 0: receive pcm highway one (dr1) is selected (default); rhs_c = 1: receive pcm highway two (dr2) is selected. rt_c[6:0] receive time slot selection for part c in three-party conference. the valid value of the rt_c[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of rt_c[6:0] is 0(d). greg13: transmit time slot and highway selection for part d in three-party conf erence, read/write (2ch/ach) ths_d transmit pcm highway selection for part d in three-party conference ths_d = 0: transmit pcm highway one (dx1) is selected (default); ths_d = 1: transmit pcm highway two (dx2) is selected. tt_d[6:0] transmit time slot selection for part d in three-party conference. the valid value of the tt_d[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of tt_d[6:0] is 0(d). greg14: receive time slot and highway selection for pa rt d in three-party confer ence, read/write (2dh/adh) rhs_d receive pcm highway selection for part d in three-party conference rhs_d = 0: receive pcm highway one (dr1) is selected (default); rhs_d = 1: receive pcm highway two (dr2) is selected. rt_d[6:0] receive time slot selection for part d in three-party conference. the valid value of the rt_d[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of rt_d[6:0] is 0(d). greg15: level meter count_number low 8 bits, read/write (2eh/aeh) the lm_cn[7:0] bits in this register toget her with the lm_cn[10:8] bits in greg16 form an 11-bit counter register, which is use d for the level meter to set the time period for pcm data sampling. the maximum number of time cycles set by the lm_cn[10:0] bits is 7ffh, corresponding to 255.875 ms. the time period for samplin g can be programmed from 0 ms to 255.875 ms in steps of 0.125 ms (8k). if the lm_cn[10:0] bits are set to be 000h (corresponding to 0 ms), the pcm data will be transmitted transparently to t he level meter result registers without being sampled. lm_cn[10:0] = 0 (d): the pcm data is transmitted to level me ter result registers greg17 and greg18 directly (default); lm_cn[10:0] = n (d):the pcm data is sampled for n ? 125 s (n from 1 to 2047). b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101011 i/o data rhs_c rt_c[6:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101100 i/o data ths_d tt_d[6:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101101 i/o data rhs_d rt_d[6:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101110 i/o data lm_cn[7:0] 70 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range greg16: level meter count_number high 3 bi ts; level meter on/off, channel selection and once/continuous m easurement, read/write (2fh/afh) lm_once execution mode of the integrator in level meter. the in tegration can be executed continuously or once after every initia - tion. lm_once = 0: the integrator runs continuously (default); lm_once = 1: the integrator runs onl y once. to start again, the lm_en bit must be set from 0 to 1 again. lm_en level meter function enable. this bit starts or stops level metering. lm_en = 0: disabled, level metering stops (default); lm_en = 1: enabled, level metering starts. lm_cs level meter channel selection. th e lm_cs[1:0] bits determine the data on which channel will be level metered. lm_cs[1:0] = 00: the data on channel 1 will be input to the level meter (default); lm_cs[1:0] = 01: the data on channel 2 will be input to the level meter; lm_cs[1:0] = 10: the data on channel 3 will be input to the level meter; lm_cs[1:0] = 11: the data on channel 4 will be input to the level meter. lm_cn level meter count number high 3 bits lm_cn[10: 8]. refer to the description of greg15 for details. greg17: level meter result regi ster (low), read only (30h) this register contains the low byte of the level me ter result. the default value of lmrl[7:0] bits is 0. greg18: level meter result regi ster (high), read only (31h) this register contains the high byte of the level meter result. the default value of the lmrh[7:0] is 0. greg19: fsk flag length register, read/write (32h/b2h) the flag signal is a stream of '1'. it is transmitted between two message bytes during the caller id data transmission. this register is used to set the number of the flag bits '1'. the value of fsk_fl[7:0] bits is valid from 0 to 255(d). the default value of 0(d) means that no flag signal will be sent out. greg20: fsk data length regi ster, read/write (33h/b3h) this register is used to set the length of the data bytes that will be transmitted except the flag signal. the value of the fsk_dl[7:0] bits is vali d from 0 to 64(d). any value larger than 64( d) will be taken as 64(d) by the dsp. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0101111 i/o data lm_once lm_en lm_cs lm_cs[0] reserved lm_cn[10:8] b7 b6 b5 b4 b3 b2 b1 b0 command00110000 i/o data lmrl[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command00110001 i/o data lmrh[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0110010 i/o data fsk_fl[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0110011 i/o data fsk_dl[7:0] 71 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range the default value of 0 means that no data bytes will be sent out. greg21: fsk seizure length re gister, read/write (34h/b4h) the seizure length is the number of '01' pairs that represent the seizure phase. the seizure length is two times of the value of the fsk_sl[7:0] bits. the value of the fsk_sl[7:0 ] bits is valid from 0 to 255( d), corre- sponding to the seizure length from 0 to 510 (d). the default value of this register is 0, t hat means no seizure signal will be sent out. greg22: fsk mark length regi ster, read/write (35h/b5h) the mark signal is a stream of '1' that will be transmitted in initial flag phase. this register is used to set the number of the mark bits ?1?. the value of the fsk_ ml[7:0] bits is valid from 0 to 255(d). the default value of 0 means that no mark signal will be sent out. greg23: fsk transmit start, mark_after_sen d, modulation standard, fsk channel sel ection, fsk enable, read/write (36h/b6h) fsk_cs fsk channel selection. the fsk_cs[1:0] bits select a channel on which the fsk signal is generated. fsk_cs[1:0] = 00: channel 1 is selected (default); fsk_cs[1:0] = 01: channel 2 is selected; fsk_cs[1:0] = 10: channel 3 is selected; fsk_cs[1:0] = 11: channel 4 is selected. fsk_en fsk function block enable. fsk_en = 0: fsk function bl ock is disabled (default); fsk_en = 1: fsk function block is enabled. fsk_bs fsk modulation standard selection fsk_bs = 0: bell 202 standard is selected (default); fsk_bs = 1: itu-t v.23 standard is selected. fsk_mas mark after send. the fsk_mas bit determines whether the fsk generator will keep on sending a mark-after-send sig- nal (a string of ?1?) after finish sending the data in the fsk-ram. fsk_mas = 0: the fsk output will be muted after sending out the data in the fsk-ram (default); fsk_mas = 1: the fsk generator sends out a mark-after-send signal after finish sending out the data in the fsk- ram. this signal will be stopped if the fsk_mas bit is set to 0. fsk_ts fsk transmission starts. fsk_ts = 0: fsk transmissi on is disabled (default); fsk_ts = 1: fsk transmission starts. the fsk_ts bit will be reset automatically after the data in the fsk-ram is finished sending. if the seizure length, the mark length and the data length are set to 0, the fsk_ts bit will be reset to 0 immediately after it is set to 1. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0110100 i/o data fsk_sl[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0110101 i/o data fsk_ml[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0110110 i/o data reserved fsk_cs[1:0] fsk_en fsk_bs fsk_mas fsk_ts 72 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range greg24: interrupt polarity selectio n register, read/write (37h/b7h) int_pol interrupt polarity selection. the int_pol bit determines the valid polarity of all the interrupt signals including the int_cha and int_chb bits in gci c/i channel. int_pol = 0: active low (default); int_pol = 1: active high. greg25: reserved this register is reserved for future use. greg26: rslic status, read (39h ); interrupt clear, write (b9h) in mpi mode, when applying a read operation to this register, t he off-hook and ground-key status of all four channels will be r ead out. if an interrupt caused by off-hook or ground- key detection is pending, reading this register will clear the interrupt. hk[3:0] off-hook status. hk[0] = 0: channel 1 is on-hook (default); hk[0] = 1: channel 1 is off-hook. hk[1] = 0: channel 2 is on-hook (default); hk[1] = 1: channel 2 is off-hook. hk[2] = 0: channel 3 is on-hook (default); hk[2] = 1: channel 3 is off-hook. hk[3] = 0: channel 4 is on-hook (default); hk[3] = 1: channel 4 is off-hook. gk[3:0] ground-key status. gk[0] = 0: no longitudinal current detected on channel 1 (default); gk[0] = 1: longitudinal current detected (ground-key or ground start) on channel 1; gk[1] = 0: no longitudinal current detected on channel 2 (default); gk[1] = 1: longitudinal current detected (ground-key or ground start) on channel 2; gk[2] = 0: no longitudinal current detected on channel 3 (default); gk[2] = 1: longitudinal current detected (ground-key or ground start) on channel 3; gk[3] = 0: no longitudinal current detected on channel 4 (default); gk[3] = 1: longitudinal current detected (ground-key or ground start) on channel 4; in gci mode, the off-hook and ground-key status are reported vi a the upstream c/i channel only. reading this register will alwa ys get a result of 00h. if an interrupt caused by off-hook or ground-key detection is pending, applying a r ead command to this register will clear the interrupt. in both mpi and gci modes, when applying a write operation to this register , all the interrupts will be cleared. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0110111 i/o data reserved int_pol reserved b7 b6 b5 b4 b3 b2 b1 b0 command r /w0111001 i/o data gk[3] hk[3] gk[2] hk[2] gk[1] hk[1] gk[0] hk[0] 73 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 5.3.3 local registers list lreg1: transmit time slot and transmit hi ghway selection, read/write (00h/80h). th is register is used for mpi mode only. ths transmit pcm highway select ion for the specified channel. ths = 0: transmit pcm highway one (dx1) is selected (default); ths = 1: transmit pcm highway two (dx2) is selected. tt[6:0] transmit time slot sele ction for the specified channel. the valid value of the tt[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of tt[6:0] is 00h for channel 1, 01h for channel 2, 02h for channel 3 and 03h for channel 4. lreg2: receive time slot and receive highway selection, read/w rite (01h/81h). this register is used for mpi mode only. rhs receive pcm highway select ion for the specified channel. rhs = 0: receive pcm highway one (dr1) is selected (default); rhs = 1: receive pcm highway two (dr2) is selected. rt[6:0] receive time slot selection for the specified channel. the valid value of the rt[6:0] bits is from 0(d) to 127(d), corresponding to time slot 0 to time slot 127. the default value of rt[6:0] is 00h for channel 1, 01h for channel 2, 02h for channel 3 and 03h for channel 4. lreg3: loopback control, read/write (02h/82h) the register is used to enable the digital and anal og loopbacks on the specified channel(s) for testing. dlb_2m digital loopback via 2m dlb_2m = 0: disabled (nor mal operation) (default); dlb_2m = 1: enabled (closed); dlb_pcm digital loopback via the pcm interface ( this loopback is available for mpi mode only ) dlb_pcm = 0: disabled (nor mal operation) (default); dlb_pcm = 1: enabled (closed); alb_1mdc analog loopback via 1m in the dc loop alb_1mdc = 0: disabled ( normal operation) (default); alb_1mdc = 1: enabled (closed); alb_2m analog loopback via 2m alb_2m = 0: disabled (nor mal operation) (default); alb_2m = 1: enabled (closed); alb_pcm analog loopback via the pcm interface ( this loopback is available for mpi mode only ) alb_pcm = 0: disabled (nor mal operation) (default); alb_pcm = 1: enabled (closed); cutoff cut off pcm receive path b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000000 i/o data ths tt[6:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000001 i/o data rhs rt[6:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000010 i/o data reserved dlb_2m dlb_pcm reserved alb_1mdc alb_2m alb_pcm cutoff 74 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range cutoff = 0: disabled, the pcm receive path is in normal operation (default); cutoff = 1: enabled, the pcm receive path is cut off. lreg4: coefficient selectio n, read/write (03h/83h) this register determines whether the defau lt values or the coefficients in coe-ram is selected for the programmable filters, to ne genera- tors and dc offset compensation. frr coefficient selection for the frequency response correction in the receive path frr = 0: coefficient in the coe-ram is selected; frr = 1: the frequency response correction in the receive path is disabled (default). grx coefficient selection for the digital gain filter in the receive path grx = 0: coefficient in the coe-ram is selected; grx = 1: the digital gain in the receive path is 0 db (default). frx coefficient selection for the frequency response correction in the transmit path frx = 0: coefficient in the coe-ram is selected; frx = 1: the frequency response correction in the transmit path is disabled (default). gtx coefficient selection for the digital gain filter in the transmit path gtx = 0: coefficient in the coe-ram is selected; gtx = 1: the digital gain in the transmit path is 0 db (default). tg coefficient selection for t he tone generators (tg1 and tg2) tg = 0: coefficient in the coe-ram is selected; tg = 1: coefficient in the rom is selected (default) (the default values are: tg1amp = 0.94 v, tg 1freq = 852 hz, tg2amp = 0.94 v, tg2freq = 1447 hz). ecf coefficient selection for the echo cancellation filter ecf = 0: coefficient in the coe-ram is selected; ecf = 1: the echo cancellation filter is disabled (default). imf coefficient selection for the impedance matching filter imf = 0: coefficient in the coe-ram is selected; imf = 1: the impedance matching fi lter is disabled (default). dc_oft compensation value selection for the offset register dc_oft = 0: the compensation value in the coe-ram is used; dc_oft = 1: the dc offset compensation value in the rom (which is 0) is used (default). lreg5: coefficient selection and filter control register, read/write (04h/84h) v90 v90 filter characteristic enable. the bit is used to select t he filter characteristic of the lowpass filter in voice signal path. the v90 filter characteristic may be selected for a m odem transmission to improv e the transmission rate and performance. v90 = 0: the v90 filter is enabled; v90 = 1: the v90 filter is disabled (default);. hpf enable/disable the highpass filter b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000011 i/o data frr grx frx gtx tg ecf imf dc_oft b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000100 i/o data v90 hpf lm_b lm_n utd signaling dc_feed rg 75 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range hpf = 0: the highpass filter is enabled (default); hpf = 1: the highpass filter is disabled. lm_b coefficient selection for the level meter bandpass filter lm_b = 0: coefficient in the coe-ram is used for the level meter bandpass filter; lm_b = 1: coefficient in the rom is used for the level meter bandpass filter (default). lm_n coefficient selection for the level meter notch filter lm_n = 0: coefficient in the coe-ram is used for the level meter notch filter; lm_n = 1: coefficient in the rom is used for the level meter notch filter (default). utd coefficient and threshold selection for the utd utd = 0: coefficient and threshold in the coe-ram are used for utd; utd = 1: coefficient and threshold in the rom are used for utd (default). signaling coefficient selection for signaling (threshol ds for off-hook, ground-key and ring trip detection) signaling = 0: coefficients in the coe-ram are used; signaling = 1: coefficients in the rom are used (refer to table - 23 on page 62 for details) (default). dc_feed coefficient selection for dc feeding characteristic dc_feed = 0: coefficient in the coe-ram is used; dc_feed = 1: coefficient in the rom is used (default). rg coefficients selection for ring generator and ramp generator rg = 0: coefficient in the coe-ram is used; rg = 1: coefficient in the rom is used (default). lreg6: codec and rslic mode contro l register, read/write (05h/85h) all eight bits in this register and the ring bit in lr eg7 are used to control the operating mode of the chipset. the higher four bits in this register and the ring bit in lreg7 are used to control the operating mode of the codec. p_down = 0: power down mode is disabled; p_down = 1: power down mode is enabled (default). standby = 0: standby mode is disabled (default); standby = 1: standby mode is enabled. active = 0: active mode is disabled (default); active = 1: active mode is enabled. ramp = 0: ramp mode is disabled (default); ramp = 1: ramp mode is enabled; the lower four bits in this register are us ed to control the operating mode of the rslic. these four bits are used for mpi mode only. (in gci mode, the scan_en and sm[2:0] bits in the downstream c/i channel byte control the operating mode of the rslic. refer to ?4.2.3.1 downstream c/i channel byte? on page 55 for details) scan_en = 0: the corresponding rslic will not be accessed (default); scan_en = 1: the corresponding rslic will be accessed. the sm[2:0] bits determine the operating mode of the rslic as shown in the following: sm[2:0] = '000': normal active mode (default); sm[2:0] = '001': external ring; sm[2:0] = '010': internal ring; b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000101 i/o data p_down standby active ramp scan_en sm[2:0] 76 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range sm[2:0] = '011': ring open; sm[2:0] = '100': tip open; sm[2:0] = '101': internal test; sm[2:0] = '110': low power standby; sm[2:0] = '111': power down. lreg7: analog gain selection, ac/dc ring trip selection, ring generator and tone generators enable, read/write (06h/86h) im_629 analog gain for impedance scaling (agis) im_629 = 0: 600 ? (only for loops with 600 ? equivalent impedance) (default); im_629 = 1: 900 ? (for all loops including those with 600 ? equivalent impedance). ring codec operating mode control bit ring = 0: ring mode is disabled (default); ring = 1: ring mode is enabled. rt_sel ac/dc ring trip selection rt_sel = 0: ac ring trip is selected (default); rt_sel = 1: dc ring trip is selected. ring_en enable the internal ring generator ring_en = 0: internal ringing stops (default); ring_en = 1: internal ringing starts. tg2_en enable tone generator 2 (tg2) tg2_en = 0: tg2 is disabled (default); tg2_en = 1: tg2 is enabled. tg1_en enable tone generator 1 (tg1) tg1_en = 0: tg1 is disabled (default); tg1_en = 1: tg1 is enabled. lreg8: ramp generator enable, level mete r path selection and notch/bandpass filter characteristic config uration, utd source selection and utd enable, read/write (07h/87h) ramp_en enable ramp generator ramp_en = 0: ramp generator is disabled (default); ramp_en = 1: ramp generator is enabled. lm_notch level meter notch/bandpass fi lter characteristic selection lm_notch = 0: notch filter charac teristic is selected (default); lm_notch = 1: bandpass filter c haracteristic is selected. lm_filt level meter filter (bandpass/notch) enable lm_filt = 0: level meter filter (b andpass/notch) is disabled (default); lm_filt = 1: level meter filter (bandpass/notch) is enabled. lm_src level meter ac/dc source selection lm_src = 0: signal from dc path is selected for level metering (default); lm_src = 1: signal from ac path is selected for level metering. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000110 i/o data reserved im_629 ring rt_sel ring_en tg2_en tg1_en b7 b6 b5 b4 b3 b2 b1 b0 command r /w0000111 i/o data ramp_en reserved lm_notch lm_filt lm_src dc_src utd_src utd_en 77 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range dc_src dc transmit/receive pat h selection for level meter dc_src = 0: signal from dc receive path is selected for level metering (default); dc_src = 1: signal from dc transmit path is selected for level metering. utd_src utd source selection utd_src = 0: signal from receive path is detected by the utd unit (default); utd_src = 1: signal from transmit path is detected by the utd unit. utd_en enable the universal tone detection unit utd_en = 0: the utd unit is disabled (default); utd_en = 1: the utd unit is enabled. lreg9: level meter source and shift fact or selection, read/write (08h/88h) k[3:0] shift factor selection for the level meter. k[3:0] = 0000: k int = 1 (default); k[3:0] = 0001: k int = 1/2; k[3:0] = 0010: k int = 1/4; k[3:0] = 0011: k int = 1/8; k[3:0] = 0100: k int = 1/16; k[3:0] = 0101: k int = 1/32; k[3:0] = 0110: k int = 1/64; k[3:0] = 0111: k int = 1/128; k[3:0] = 1000: k int = 1/256; k[3:0] = 1001: k int = 1/512; k[3:0] = 1010: k int = 1/1024; k[3:0] = 1011 to 1111: k int = 1/2048; lm_sel[3:0] source selection for dc level meter lm_sel[3:0] = 0000: dc voltage on vtdc is selected (default); lm_sel[3:0] = 0100: dc out voltage on dcn-dcp is selected; lm_sel[3:0] = 1001: dc voltage on vl is selected; lm_sel[3:0] = 1010: voltage on io3 is selected; lm_sel[3:0] = 1011: voltage on io4 is selected; lm_sel[3:0] = 1100: voltage on rtin is selected; lm_sel[3:0] = 1101: vdd/2 is selected; lm_sel[3:0] = 1110: vcm (offset of encoding) is selected; lm_sel[3:0] = 1111: voltage on io4-io3 is selected; lreg10: level meter threshold, rectifier on /off, gain factor, read/write (09h/89h) othre over threshold indication for le vel meter. this bit is read only. othre = 0: the level meter result is below the threshold (default); othre = 1: the level meter result is over the threshold. lm_gf additional gain factor for level meter lm_gf = 0: no additional gain factor is selected (default); lm_gf = 1: additional gain factor of 16 is selected. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0001000 i/o data k[3:0] lm_sel[3:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0001001 i/o data othre lm_gf lm_rect reserved lm_th[2:0] 78 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range lm_rect enable the rectifier in the level meter. lm_rect = 0: the rectifier is disabled (default); lm_rect = 1: the rectifier is enabled. lm_th[2:0] level meter threshold selection. if the absolute value of the level meter result exceeds the selected threshold, the othre bit will be set to 1. lm_th[2:0] = 000: threshold is 0.0% (default); lm_th[2:0] = 001: threshold is 12.5%; lm_th[2:0] = 010: threshold is 25.0%; lm_th[2:0] = 011: threshold is 37.5%; lm_th[2:0] = 100: threshold is 50.0%; lm_th[2:0] = 101: threshold is 62.5%; lm_th[2:0] = 110: threshold is 75.0%; lm_th[2:0] = 111: threshold is 87.5%. lreg11: debounce filter config uration, read/write (0ah/8ah) db[3:0] debounce interval selection for off-hook and ground-key detection. the debounce interval is programmable from 0.125 ms to 2 ms in steps of 0.125 ms, corresponding to the minimal debounce time of from 2 ms to 30 ms. db[3:0] = 0000: the debounce interval is 0.125 ms, the minimal debounce time is 2 ms (default); db[3:0] = 0001: the debounce interval is 0.250 ms, the minimal debounce time is 4 ms; db[3:0] = 0010: the debounce interval is 0.375 ms, the minimal debounce time is 6 ms; ... ... ... ... ... ... db[3:0] = 1110: the debounce interval is 1.875 ms, the minimal debounce time is 30 ms; db[3:0] = 1111: the debounce interval is 2 ms, the minimal debounce time is 32 ms. ( note: during operating mode switching, there might be a narro w pulse of about 15 ms occurring on vtdc, resulting in a false interrupt to be generated. if this happens, please set db [3:0] to 0111b or above to filter this noise pulse.) db_io[3:0] io pins debounce time selection (only effective for those io pins used as digital inputs).the io pins debounce time is programmable from 2.5 ms to 32.5 ms in steps of 2 ms. db_io[3:0] = 0000: the minimal debounc e time is 2.5 ms (default); db_io[3:0] = 0001: the minimal debounce time is 4.5 ms; db_io[3:0] = 0010: the minimal debounce time is 6.5 ms; ... ... ... ... db_io[3:0] = 1110: the minimal debounce time is 30.5 ms; db_io[3:0] = 1111: the minimal debounce time is 32.5 ms. lreg12: pcm data low byte register, read only (0bh) . this register is used for mpi mode only. this register is used for the master proce ssor to monitor the transmit (a to d) pcm data. for linear code, the low byte of pcm data is sent to this register before it is trans mitted to the pcm encoder in the transmit pat h. for compressed code, the total pcm data is sent to this register before it is transmitted to the pcm encoder in the transmit path. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0001010 i/o data db[3:0] db_io[3:0] b7 b6 b5 b4 b3 b2 b1 b0 command00001011 i/o data pcm[7:0] 79 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range lreg13: pcm data high byte register, read only (0ch) . this register is used for mpi mode only. this register is used for the master proces sor to monitor the transmit (a to d) pcm data. for linear code, the high byte of pcm data is sent to this register before it is transmi tted to the pcm encoder in the transmit path. for compressed code, this register is n ot used (in this case, when read, a data byte of 00h will be read out). lreg14: utd rtime register, read/write (0dh/8dh) this register is used to set the utd recognition time (rtime): utd_rt[7:0] = rtime (ms)/16 the default value of utd_rt[7:0] is 13h. rtime must be multiples of 16 ms. the range of it is: 0 ms rtime 4000 ms. lreg15: utd rbktime register, read/write (0eh/8eh) this register is used to set the utd recognition break time (rbktime): utd_rbk[7:0] = rbktime (ms)/4 the default value of utd_rbk[7:0] is 19h. rbktime must be multiples of 4 ms. the range of it is: 0 ms rbktime 1000 ms. lreg16: utd etime register, read/write (0fh/8fh) this register is used to set t he utd end detection time (etime): utd_et[7:0] = etime (ms)/4 the default value of utd_et[7:0] is 40h. etime must be multiples of 4 ms. the range of it is: 0 ms etime 1000 ms. lreg17: utd ebrktime, read/write (10h/90h) this register is used to set the utd end detection break time (ebrktime): utd_ebrk[7:0] = ebrktime (ms) the default value of utd_ebrk[7:0] is 64h. the range of the ebrktime is: 0 ms ebrktime 255 ms. b7 b6 b5 b4 b3 b2 b1 b0 command00001100 i/o data pcm[15:8] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0001101 i/o data utd_rt[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0001110 i/o data utd_rbk[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0001111 i/o data utd_et[7:0] b7 b6 b5 b4 b3 b2 b1 b0 command r /w0010000 i/o data utd_ebrk[7:0] 80 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range lreg18: interrupt mask register, read/write (11h/91h) gk_m mask bit for the ground-key status bits gk[3:0] in greg26 gk_m = 0: each change of the gk[3:0] bits generates an interrupt; gk_m = 1: changes of the gk[3:0] bits do not generate interrupts (default). hk_m mask bit for the off-hook status bits hk[3:0] in greg26 hk_m = 0: each change of the hk[3:0] bits generates an interrupt; hk_m = 1: changes of the hk[3:0] bits do not generate interrupts (default). otmp_m mask bit for the over temper ature status bit otmp in lreg21 otmp_m = 0: changes of the otmp bit from 0 to 1 generate interrupts; otmp_m = 1: changes of the otmp bit from 0 to 1 do not generate interrupts (default). ramp_m mask bit for the ramp_ok bit in lreg21 ramp_m = 0: changes of the ramp_ok bi t from 0 to 1 generate interrupts; ramp_m = 1: changes of the ramp_ok bit from 0 to 1 do not generate interrupt (default). gkp_m mask bit for the gk_pol bit in lreg21 gkp_m = 0: each change of the gk_pol bit generates an interrupt; gkp_m = 1: changes of the gk_pol bit do not generate interrupts (default). lreg19: io interrupt mask regi ster, read/write (12h/92h) rev_pol reverse the polarity of dc feeding rev_pol = 0: normal polarity (default); rev_pol = 1: reverse polarity. sync_en enable synchronous ringi ng for external ringing mode. sync_en = 0: asynchronous external ringing is selected (default); sync_en = 1: external ringing with zero-crossing is selected; io_m[3:0] mask bits for the io status bits io[3:0] in r egister lreg19 when the io pins are configured as inputs. io_m[3] = 0: each change of the io[3] bit generates an interrupt; io_m[3] = 1: changes of the io[3] bi t do not generate interrupts (default). io_m[2] = 0: each change of the io[2] bit generates an interrupt; io_m[2] = 1: changes of the io[2] bi t do not generate interrupts (default). io_m[1] = 0: each change of the io[1] bit generates an interrupt; io_m[1] = 1: changes of the io[1] bi t do not generate interrupts (default). io_m[0] = 0: each change of the io[0] bit generates an interrupt; io_m[0] = 1: changes of the io[0] bi t do not generate interrupts (default). b7 b6 b5 b4 b3 b2 b1 b0 command r /w0010001 i/o data reserved gk_m hk_m otmp_m ramp_m gkp_m b7 b6 b5 b4 b3 b2 b1 b0 command r /w0010010 i/o data reserved rev_pol sync_en io_m[3] i o_m[2] io_m[1] io_m[0] 81 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range lreg20: rslic io direction configuration and io status register, read/write (13h/93h) io_c[3:0] rslic io direction configuration. the io_c[3:0] bits determine the directions of the io4 to io1 pins, respectively. io_c[3] = 0: the io4 pin of the specified channel is configured as an input (default); io_c[3] = 1: the io4 pin of the specif ied channel is configured as an output. io_c[2] = 0: the io3 pin of the specified channel is configured as an input (default); io_c[2] = 1: the io3 pin of the specif ied channel is configured as an output. io_c[1] = 0: the io2 pin of the specified channel is configured as an input (default); io_c[1] = 1: the io2 pin of the specif ied channel is configured as an output. io_c[0] = 0: the io1 pin of the specified channel is configured as an input (default); io_c[0] = 1: the io1 pin of the specif ied channel is configured as an output. io[3:0] io pin status (when the corresponding io pin is configured as an input) or io control data (when the corresponding io pin is configured as an output) io[3] = 0: the io4 pin of the specified channel is in logi c low state (when configured as an input) or it is set to logic low (when configured as an output); io[3] = 1: the io4 pin of the specifi ed channel is in logic high state (when co nfigured as an input) or it is set to logic high (when configured as an output); io[2] = 0: the io3 pin of the specified channel is in logi c low state (when configured as an input) or it is set to logic low (when configured as an output); io[2] = 1: the io3 pin of the specifi ed channel is in logic high state (when co nfigured as an input) or it is set to logic high (when configured as an output); io[1] = 0: the io2 pin of the specified channel is in logi c low state (when configured as an input) or it is set to logic low (when configured as an output); io[1] = 1: the io2 pin of the specifi ed channel is in logic high state (when co nfigured as an input) or it is set to logic high (when configured as an output); io[0] = 0: the io1 pin of the specified channel is in logi c low state (when configured as an input) or it is set to logic low (when configured as an output); io[0] = 1: the io1 pin of the specifi ed channel is in logic high state (when co nfigured as an input) or it is set to logic high (when configured as an output); once the ion pin is configured as an i nput, each change of the corresponding io[n] bit will generate an interrupt if the mask b it io_m[n] in lreg19 is set to 0. a read command to this register wi ll clear the interrupt caused by changes of the io[3:0] bits. lreg21: interrupt source register, read only (14h) feed_i dc feeding characteri stic indication bit for th e constant current zone. whenever the dc feeding is operated at the constant zone, t he feed_i is set to 1, otherwise it is set to 0. feed_v dc feeding characteri stic indication bit for the constant voltage zone. whenever the dc feeding is operated at the constant voltage zone, th e feed_v bit it is set to 1, otherwise it is set to 0. feed_r dc feeding characteristic i ndication bit for the resistive zone. whenever the dc feeding is operated at the resistive zone, t he feed_r bit is set to 1, otherwise it is set to 0. b7 b6 b5 b4 b3 b2 b1 b0 command r /w0010011 i/o data io_c[3] io_c[2] io_c[1] io_c[0] io[3] io[2] io[1] io[0] b7 b6 b5 b4 b3 b2 b1 b0 command00010100 i/o data feed_i feed_v feed_r lm_ok utd_ok otmp ramp_ok gk_pol 82 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range lm_ok indicating whether the level metering is finished. changes of this bit from 0 to 1 generate interrupts (the lm_ok bit has no mask bit). lm_ok = 0: level meter result is not ready (default); lm_ok = 1: level meter result is ready. utd_ok utd result indication. changes of this bit from 0 to 1 generate interr upts (the utd_ok bit has no mask bit). utd_ok = 0: no special tone signal (e .g., fax/modem) is detected (default); utd_ok = 1: special tone signal (e.g., fax/modem) is detected otmp over temperature detection result. changes of this bit from 0 to 1 generate interr upts if the mask bit otmp_m in register lreg18 is set to 0. otmp = 0: temperature at the rslic is below the limit (default); otmp = 1: temperature at t he rslic is above the limit; ramp_ok indicating whether ramp generation is completed. changes of this bit from 0 to 1 generate interrupts if the mask bit ramp_m in register lreg18 is set to 0. when the ramp generator starts a new generation, the ramp_ok bit will be reset to 0. ramp_ok = 0: ramp generation is not completed (default); ramp_ok = 1: ramp generation is completed; gk_pol ground-key polarity, indicating the ac tive ground-key threshold (positive or negative). changes of this bit generate inte r- rupts if the mask bit gkp_m in register lreg18 is set to 0. gk_pol = 0: negative ground-key threshold is active; gk_pol = 1: positive ground-key th reshold is active (default); applying a read command to this register wi ll clear the interrupt caused by the valid change of the lm_ok, utd_ok, otmp, ramp_o k or gk_pol bit. 83 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 5.4 programming examples 5.4.1 programming examples for mpi mode 5.4.1.1 example of programming the local registers via mpi ? writing to lreg2 and lreg1 of channel 1: 1010,0011 channel enable command 0001,0010 data for greg4 (channel 1 is enabled for programming) 1000,0001 local register write command (the address is '00001', means that data will be written to lreg2 and lreg1.) 0000,0001 data for lreg2 0000,0000 data for lreg1 ? reading lreg2 and lreg1 of channel 1: 1010,0011 channel enable command 0001,0010 data for greg4 (channel 1 is enabled for programming) 0000,0001 local register read command (the address is '00001', means that lreg2 and lreg1 will be read.) after the preceding commands are execut ed, data will be sent out as follows: 1000,0001 identification code 0000,0001 data read out from lreg2 0000,0000 data read out from lreg1 figure - 36 waveform of programming example: writing to local registers figure - 37 waveform of programmin g example: reading local registers ci cclk cs channel enable command channel enable data local command data for lreg2 data for lreg1 ci cclk cs channel enable command channel enable data local command data read out from lreg2 data read out from lreg1 co identification code high 'z' high 'z' 84 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 5.4.1.2 example of programming the global registers via mpi since the global registers are shared by all four channels, it is no need to specif y the channel(s) before addressing global re gisters. except for this, programming global registers are the same as programming local registers. refer to ?5.4.1.1 example of programmi ng the local registers via mpi? on page 83 for more information. 5.4.1.3 example of programming the coefficient-ram via mpi ? writing to the coe-ram of channel 1: 1010,0011 channel enable command 0001,0010 data for greg4 (channel 1 is enabled for programming) 1110,0000 coe-ram write command (the address of '00000' is located in block 1, means that data will be written to block 1.) byte 1 data for high byte of word 8 in block 1 (the highest two bits (b7b6) are ignored) byte 2 data for low byte of word 8 in block 1 byte 3 data for high byte of word 7 in block 1 (the highest two bits (b7b6) are ignored) byte 4 data for low byte of word 7 in block 1 byte 5 data for high byte of word 6 in block 1 (the highest two bits (b7b6) are ignored) byte 6 data for low byte of word 6 in block 1 byte 7 data for high byte of word 5 in block 1 (the highest two bits (b7b6) are ignored) byte 8 data for low byte of word 5 in block 1 byte 9 data for high byte of word 4 in block 1 (the highest two bits (b7b6) are ignored) byte 10 data for low byte of word 4 in block 1 byte 11 data for high byte of word 3 in block 1 (the highest two bits (b7b6) are ignored) byte 12 data for low byte of word 3 in block 1 byte 13 data for high byte of word 2 in block 1 (the highest two bits (b7b6) are ignored) byte 14 data for low byte of word 2 in block 1 byte 15 data for high byte of word 1 in block 1 (the highest two bits (b7b6) are ignored) byte 16 data for low byte of word 1 in block 1 ? reading from the coe-ram of channel 1: 1010,0011 channel enable command 0001,0010 data for greg4 (channel 1 is enabled for programming) 0110,0000 coe-ram read command (the address of '00000' is loca ted in block 1, means that block 1 will be read.) after the preceding commands are executed, data will be sent out as follows: 1000,0001 identification code byte 1 data read out from high byte of word 8 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 2 data read out from low byte of word 8 in block 1 byte 3 data read out from high byte of word 7 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 4 data read out from low byte of word 7 in block 1 byte 5 data read out from high byte of word 6 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 6 data read out from low byte of word 6 in block 1 byte 7 data read out from high byte of word 5 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 8 data read out from low byte of word 5 in block 1 byte 9 data read out from high byte of word 4 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 10 data read out from low byte of word 4 in block 1 byte 11 data read out from high byte of word 3 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 12 data read out from low byte of word 3 in block 1 byte 13 data read out from high byte of word 2 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 14 data read out from low byte of word 2 in block 1 byte 15 data read out from high byte of word 1 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 16 data read out from low byte of word 1 in block 1 5.4.1.4 example of programming the fsk-ram via mpi ? writing to the fsk-ram: 1100,0001 fsk-ram write command (the address is '00001', means that data will be written to word 2 and word 1.) byte 1 data for high byte of word 2 byte 2 data for low byte of word 2 byte 3 data for high byte of word 1 byte 4 data for low byte of word 1 85 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range ? reading from the fsk-ram: 0100,0001 fsk-ram read command (the address is '00001', means that word 2 and word 1 will be read.) after this command is executed, data will be sent out as follows: 1000,0001 identification code byte 1 data read out from high byte of word 2 byte 2 data read out from low byte of word 2 byte 3 data read out from high byte of word 1 byte 4 data read out from low byte of word 1 5.4.2 programming examples for gci mode 5.4.2.1 example of programming the local registers via gci ? writing to lreg2 and lreg1 of channel 1: 1000,0001 program start command (provi ded channel a is the destination) 1000,0001 local register write command (the address is '00001', means that data will be written to lreg2 and lreg1.) 0000,0001 data for lreg2 0000,0000 data for lreg1 ? reading from lreg2 and lreg1 of channel 1: 1000,0001 program start command (provi ded channel a is the source) 0000,0001 local register read command (the address is '00001', means that lreg2 and lreg1 will be read.) after the preceding commands are execut ed, data will be read out as follows: 1000,0001 program start byte 0000,0001 data read out from lreg2 0000,0000 data read out from lreg1 5.4.2.2 example of programming the global registers via gci in gci mode, the global registers ar e addressed in the similar manner as the local registers except the a /b bit in the program start byte is neglected. see the descriptions above for details. 5.4.2.3 example of programming the coefficient-ram via gci ? writing to the coe-ram of channel 1: 1000,0001 program start command (provided channel a is the destination) 1110,0000 coe-ram write command (the address is '00001', means that data will be written to block 1.) byte 1 data for high byte of word 8 in block 1 (the highest two bits (b7b6) are ignored) byte 2 data for low byte of word 8 in block 1 byte 3 data for high byte of word 7 in block 1 (the highest two bits (b7b6) are ignored) byte 4 data for low byte of word 7 in block 1 byte 5 data for high byte of word 6 in block 1 (the highest two bits (b7b6) are ignored) byte 6 data for low byte of word 6 in block 1 byte 7 data for high byte of word 5 in block 1 (the highest two bits (b7b6) are ignored) byte 8 data for low byte of word 5 in block 1 byte 9 data for high byte of word 4 in block 1 (the highest two bits (b7b6) are ignored) byte 10 data for low byte of word 4 in block 1 byte 11 data for high byte of word 3 in block 1 (the highest two bits (b7b6) are ignored) byte 12 data for low byte of word 3 in block 1 byte 13 data for high byte of word 2 in block 1 (the highest two bits (b7b6) are ignored) byte 14 data for low byte of word 2 in block 1 byte 15 data for high byte of word 1 in block 1 (the highest two bits (b7b6) are ignored) byte 16 data for low byte of word 1 in block 1 ? reading from the coe-ram of channel 1: 1000,0001 program start command (provided channel a is the source) 0110,0000 coe-ram read command (the address is ' 00000', means that block 1 will be read.) after these commands are executed, data will be sent out as follows: 1000,0001 program start byte byte 1 data read out from high byte of word 8 in block 1 (the highest two bi ts (b7b6) are meaningless) 86 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range byte 2 data read out from low byte of word 8 in block 1 byte 3 data read out from high byte of word 7 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 4 data read out from low byte of word 7 in block 1 byte 5 data read out from high byte of word 6 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 6 data read out from low byte of word 6 in block 1 byte 7 data read out from high byte of word 5 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 8 data read out from low byte of word 5 in block 1 byte 9 data read out from high byte of word 4 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 10 data read out from low byte of word 4 in block 1 byte 11 data read out from high byte of word 3 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 12 data read out from low byte of word 3 in block 1 byte 13 data read out from high byte of word 2 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 14 data read out from low byte of word 2 in block 1 byte 15 data read out from high byte of word 1 in block 1 (the highest two bi ts (b7b6) are meaningless) byte 16 data read out from low byte of word 1 in block 1 5.4.2.4 example of programming the fsk-ram via gci ? writing to the fsk-ram: 100x,0001 program start command 1100,0001 fsk-ram write command (the address is '00001', means that data will be written to word 2 and word 1.) byte 1 data for high byte of word 2 byte 2 data for low byte of word 2 byte 3 data for high byte of word 1 byte 4 data for low byte of word 1 ? reading from the fsk-ram: 100x,0001 program start command 0100,0001 fsk-ram read command (the address is '00001', means that word 2 and word 1 will be read.) after the preceding commands are execut ed, data will be sent out as follows: 100x,0001 program start byte byte 1 data read out from high byte of word 2 byte 2 data read out from low byte of word 2 byte 3 data read out from high byte of word 1 byte 4 data read out from low byte of word 1 87 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 6 operational description 6.1 operating modes in many applications, the system power consumption is an important parameter. for large and remotely f ed systems, this parameter is more critical and must be limited to a given value to meet cooling requirements and save power. generally, the system power dissi pation is determined mainly by the high-voltage part. the most effective power-saving method is to limit slic functionality and reduce supply voltage in line according to different requirements. the rslic- codec chipset achieves this goal by providing different operating modes according to different loop states or testing requirements. see the following descriptions for details. 6.1.1 rslic control signaling the codec provides three common mode selection pins m1 to m3 and four individual chip selection pins cs1 to cs4 for the four rslics to control their operating modes. see figure - 38 for details. the cs1 to cs4 pins of the co dec are ternary logic pins as illustrated in the following: csn = 0: the codec will send mode control data to the rslicn through the m1 to m3 pins. csn = 1: the codec will receive the temperature information of the rslicn through the m3 pin. csn = 1.5 v: the codec will not send or receive data to/from the rslicn through the m1 to m3 pins. note that the m3 pin of the code c is bidirectional. its direction is determined by the active csn as described above. figure - 39 shows the rslic control timing diagram. figure - 38 rslic mode control signaling m1~m3 cs1 cs2 cs3 m1~m3 cs cs rslic 1 # codec m1~m3 cs rslic 2 # m1~m3 cs rslic 3 # m1~m3 cs rslic 4 # cs4 88 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range figure - 39 rslic control timing diagram m3 i/o control m3 m2 m1 cs4 cs3 cs2 cs1 fs 125 s 31.25 s 7.8125 s output output output output input input input input 89 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 6.1.2 rslic operating modes the rslics can be operated in nine different modes as shown in table - 26 . the operating mode is configured by the sm[2:0] bits in lreg6 (mpi mode) or in the dow nstream c/i channel (gci mode). the scan_en bit in lreg6 (mpi mode) or downstream c/i channel (gci mode) determines whether the corresponding rslic will be accessed. if this bit is set to 1, the rslic will receive data from the codec when the corresponding csn pin is logic low and transmit data to the codec when the correspondi ng csn pin is logic high (as illustrated in figure - 39 ). if this bit is set to 0, the corresponding csn pin will be set to 1.5 v and the rslic will not be accessed. ?normal active in this mode, a regular call can be performed. voice can be transferred via the telephone line. besides providing low-impedance voltage (vbl) feeding to the line, the rslic senses, scales and separates transversal and longitudinal line currents. ? external ring the rslic receives an external ri nging signal provided at pins rsp and rsn and feeds it to the telephone line. the rslic also provides a ring trip signal for the codec via the rt pin. ? internal ring the codec generates a balanced ringing signal and outputs it to the rslic through the dcp and dcn pins. the rslic amplifies this ringing signal and feeds it to the telephone line. ? ring open in ring open mode, the ring power amplifier is switched off and the ring terminal presents a high impedanc e to the line. this mode is used to measure the leakage current tip/gnd. ? tip open in tip open mode, the tip power ampl ifier is switched off and the tip terminal presents a high impedance to the line. this mode is used for ground-key detection and the leakage current ring/gnd measurement. ? internal test this mode can be used to test the rslic-codec chipset without external circuits. when the rslic is set to internal test mode, it works in a similar way as normal active mode. the only differ ence is that a built-in resistor will be connected between the tip and ring pins to form a loop for testing. see figure - 40 for details. ? low power standby in this mode, all functions except off-hook detection are switched off to reduce power consumption. two 2.5 k ? resistors are connected from tip to bgnd and from ring to vbat respectively. a simple sense circuit monitors the dc current flowing through these resistors. by calculating the transversal dc curr ent and feeding it to the codec, off- hook can be detected. once the s ubscriber goes off-hook, the whole chipset should be activated and put into active mode. ? power down in this mode, all functions ar e disabled, including the off-hook detection. the tip and ring power amplif iers are both switched off so that the power consumption is minimal. ? overtemp check in this mode, the rslic will report the temperature state of itself to the codec through the m3 pin. this temperature state will be indicated by the otmp bit in lreg21. if t he temperature exceeds the limit (150 o c), the rslic will be automatically shut down. every time the otmp bit changes from 0 to 1, r epresenting the temperature of the rslic becoming overloaded, an interr upt will be generated if the otmp bit is not masked by the otmp_m bit in lreg18. 6.1.3 codec operating modes the codec can work in five modes: power down, standby, active, ramp and ring. these modes are enabled by setting the p_down, standby, active and ramp bits in lreg6 and ring bit in lreg7 respectively. ? power down this mode is applicable for the line (c hannel) that is not in use. in this mode, all functions of the codec are switched off so that the power dissipation can be minimized. both ac and dc loops are inactive, no current is fed to the line and the hook switch can not be detected. each channel of the codec c an be powered down individually by setting the p_down bit in corr esponding lreg6. if four channels are powered down, the clock cycles fed to the mclk and bclk pins should be shut off to achieve the lowest power consumption. the codec can be changed from power down mode to any other modes by properly setting lreg6 and lreg7. table - 26 rslic operating mode rslic operating mode rslic mode control pins cs m3 m2 m1 normal active 0 0 0 0 external ring 0 0 0 1 internal ring 0 0 1 0 ring open 0 0 1 1 tip open 0 1 0 0 internal test 0 1 0 1 low power standby 0 1 1 0 power down 0 1 1 1 overtemp check (read) 1 x 1 1 figure - 40 rslic internal test circuit r s tis tip ring ris r s rslic 2 k 90 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range ? standby the standby mode is applicable for sy stem state of subscriber being on-hook. in this mode, only the ac loop is active, all functions except for the off-hook detection are switched off. the sensed voltage from the rslic is fed to an analog comparator in the codec via vtac pin. the loop state can be determined by co mparing the sensed voltage with a fixed off-hook threshold. if off-hook st ate is detected, the overall circuits should be activated and switched to the active mode. ?active the active mode corresponds to the system state of off-hook. in this mode, both ac and dc loops are ac tive. the rslic provides low- impedance voltage (vbl) fed to the line. the rslic senses the transversal and longitudinal line cu rrents and separates the transversal current to ac and dc parts. the codec scales the currents and converts the ac part of the transversal current to voice data. on the other hand, the codec expands the voice data from the pcm bus and converts them to an analog signal. the dc voltage fed to the line can be automatically achieved by the chipse t according to certain loop lengths, power optimized solution. ?ring this mode corresponds to the system state of ringing. the chipset provides both internal ringing and ex ternal ringing modes to be selected. refer to table - 26 for details. if internal ringing mode is sele cted, an internal balanced ringing signal of up to 70 vp (with high voltage battery (vbh) of 70 v) can be generated without any external component s. in applications that high ringing voltage is not needed, a dc offset can be added to support the dc ring trip detection, which is more reliable than ac ring trip detection. if an external ring generator and ring relays are used, the rslic can be switched to power down mode. an individual operation amplifier in the rslic is supplied for ring trip detection. ?ramp if ramp mode is selected (lreg6: ramp = 1), the integrated ramp generator in the codec is active and able to generate a ramp signal to help measuring the capacitance. the ramp generator is fully programmable. by programming the ra mp slope, ramp start voltage and end voltage, a desired ramp can be generated by the codec and output to the line via the rlsic. with this ramp signal as the source, the line capacitance can be measured via the dc level meter. see ?3.9.6.5 capacitance measurement? on page 47 for detailed information. 6.2 pll power down the pll_pd bit in greg1 is used to power down the pll block of the codec to reduce the power consumption. if the pll_pd bit is set to 1, the pll block is turned off and the dsp operation is disabled. as described above, each of the cha nnels can be individually powered down by setting the corresponding p_ down bit in lreg6 to 1. when all four channels and the pll block are powered down, the lowest power consumption can be achieved. 6.3 programmable i/os of the codec the codec provides four progr ammable io pins per channel as shown in the following: io1: io pin with relay-driving capability io2: io pin with relay-driving capability io3: io pin with analog input capability io4: io pin with analog input capability the four io pins io4 to io1 can be independently configured as input or output by the corresponding control bits io_c[3] to io_c[0] in lreg20. if the io pins are configured as inputs, the status of the io pins will be indicated by the io[3:0] bits in lr eg20. if the io pins are configured as outputs, the data written in the io[3:0] bits in lreg20 will be sent out through the io pins. if the io1 and io2 pins are configur ed as outputs, they are capable of driving external relays. based on this , the io1 pin automatically acts as an output to control the external ring relay when external ringing mode is selected. refer to ?3.4.2 external ringing mode? on page 24 for details. if the io3 and io4 pins are configur ed as inputs, they are capable of receiving analog inputs. with this c apability external voltages can be fed to the dc level meter via the io3 and/or io4 pins to be measured. refer to ?3.9.6.6 voltage measurement? on page 48 for details. the input signals from the four io s will be filtered by a programmable debounce filter (see figure - 41 ). the output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the db_io[3:0] bits in lreg11. the debounce period is progr ammable from 0 ms to 30 ms in steps of 2 ms, corresponding to the minimal debounce time of 2.5 ms to 32.5 ms (a delay time of about 2.5 ms added). the default value of db_io[3:0] is ?0000?. figure - 41 io debounce filter db_io[3:0] debounce period (0 ? 30ms) 8 bit debounce counter debounced io io fs q d rst q q q ddd q d en 91 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range the debounced io data are stored in the io[3:0] bits in lreg20. the four bits io[3] to io[0] have their respective mask bits - io_m[3] to io_m[0] in lreg19. each change of the io[n] bit will generate an interrupt if its mask bit io_m[n] is set to 0 (n = 0 to 3). 6.4 interrupt handling the rslic-codec chipset is capable of generating interrupts for the following event: ? off-hook/on-hook detected ? ground-key detected ? ground-key polarity changed ? ring trip detected ? io status changed ? over temperature detected ? level metering finished ? special tone detected ? ramp generation finished the interrupt status register gr eg26 contains the results of hook/ ring trip detection and ground-key detection for four channels (two bits per channel). other interrupt status of each channel is contained by the respective interrupt status registers lreg20 and lreg21 (each interrupt function has one bit). thes e bits are set when an interrupt is pending for the associated source. two interrupt mask registers (lreg18 and lreg19) per channel contain one mask bit for each of the above interrupt functions except special tone detected and level metering completed. if a mask bit is set to high, the corresponding interrupt will be masked. refer to table - 27 for detailed information. in mpi mode, the interrupt output pin int /int will be set to active level if any interrupt is generated. in gci mode, if any interrupt is generated in a channel, the corresponding int_cha or int_chb bit in upstream c/i channel will be set to acti ve level. the valid polarity of the int /int pin and the int_cha, int_chb bits is determined by the int_pol bit in register greg24 as shown below: int_pol = 0: active low; int_pol = 1: active high. in both mpi and gci mode, the pending interrupts can be cleared by a read operation on the corresponding interrupt register. for example, reading greg26 clears the interrupts generated by hook/ring trip detection and ground-key detection. addi tionally, the codec provides a dedicated command to clear all the interrupts at one time. that is, by applying a write operation to greg26, all the global and local interrupt status registers will be cleared. a hardware or power-on reset of the codec clears all interrupt status registers and resets the int /int pin to inactive (mpi mode) or resets the int_cha and int_chb bi ts in the gci c/i channel (gci mode). a software reset applied to one channel clears all local interrupt status registers of that channel but does not effect those of the other channels and the global interrupt status register. 6.5 signal path and test loopbacks figure - 42 on the following page shows the main ac and dc signal paths and the integrated analog and digital loopbacks inside the codec. refer to the register descriptions on greg6 and lreg3 for details. table - 27 interrupt s ource and interrupt mask interrupt source status bits interr upt generating conditions mask bit hook status hk[n] bit in greg26 (n = 0 to 3) each change of the hk[n] bit hk_m bit in lreg18 ground-key status gk[n] bit in greg26 (n = 0 to 3) each change of the gk[n] bit gk_m bit in lreg18 ring trip status hk[n] bit in greg26 (n = 0 to 3) each change of the hk[n] bit hk_m bit in lreg18 rslic io status io[n] bit in lreg20 (n = 0 to 3) each change of the io[n] bit when the corresponding io pin is configured as an input io_m[n] bit in lreg19 ground-key polarity gk_pol bit in lreg21 each change of the gk_pol bit gkp_m bit in lreg18 over temperature status otmp bit in lreg21 a change of the otmp bit from 0 to 1 otmp_m bit in lreg18 ramp generation ramp_ok bit in lreg21 a change of the ramp_ok bit from 0 to 1 ramp_m bit in lreg18 utd result utd_ok bit in lreg21 a change of the utd_ok bit from 0 to 1 none level meter sequence lm_ok bit in lreg21 a change of the lm_ok bit from 0 to 1 none 92 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range figure - 42 ac/dc signal path and test loopbacks anti-alias filter (aaf) sigma-delta modulator (sdm) gain transmit (gtx) low-pass filter transmit 2nd decimation filter frequency response correction transmit (frx) high-pass filter transmit (hpf) 2nd interpolation filter gain receive (grx) 3rd interpolation filter impedance matching filter (imf) transhbrid balance filter (ecf) 1st interpolation filter 1st decimation filter pcm encoder pcm decoder frequency response correction receive (frr) low-pass filter receive sigma-delta demodulator (d-sdm) smoothing filter & scf gain for impedance scaling (gis) analog gain for impedance scaling (agis) utd tg1 tg2 cutoff time slot assignment time slot assignment dlb_2m alb_2m dlb_64k alb_64k dlb_8k alb_8k sel utd_en utdsrc dlb_pcm alb_pcm utd_ok dlb_di alb_di gkd comparator mux adc 1.024mhz dc1 loop filter(dc) pofil dac interp ring generator loop feeding algorithm hook detection dc offset ring trip detector ramp generator ramp_ok hook indication revpol dc2 level meter sel dc_src lm_src dcn/ dcp vcm vdd io4-io3 io4 io3 vtdc vref vl ringdc rtin "0" "1" "0" rtp offset bandpass/ notch filter lm_filt vl alb_1mdc sel acp/ acn vtac dx1/dx2 dr1/dr2 analog @2mhz @16khz @64khz @8khz ts pcm highway "1" off-hook comparator vref lmout greg6: lreg3: msb lsb msb lsb these loopbacks are controlled by registers greg6 and lreg3 as shown below. each of the loopbacks is closed by setting the corr esponding bit to 1 and opened by setting the corresponding bit to 0. note that the four loopbacks alb_di, dlb_di, alb_pcm and d lb_pcm are available for mpi mode only. reserved alb_64k alb_8k alb_di reserved dlb_64k dlb_8k dlb_di reserved dlb_2m dlb_pcm reserved alb_1mdc alb_2m alb_pcm cutoff 93 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 6.6 rslic power on sequence it is recommended to power on the rslic following the sequence below: 1. apply ground to the agnd and bgnd pins; 2. apply +3.3 v power supply to the vdd pin; 3. apply battery voltage ( ? 70 v vbh ? 52 v) to the vbh pin; 4. apply battery voltage ( ? 52 v vbl ? 20 v) to the vbl pin; but if the recommended application circuit ( figure - 49 on page 104 or figure - 50 on page 105 ) is used, the above mentioned rslic power on sequence is not necessary. 6.7 codec power on sequence to power on the codec, the operating sequence should be as follows: 1. apply ground to all ground pins; 2. apply vdd voltage to all power supply pins; 3. select master cloc k frequency (via greg4); 4. program filter coefficients and other parameters as required. 6.8 default state after reset 6.8.1 power-on reset and hardware reset the codec can be reset by a power-on reset or a hardware reset. a hardware reset of the codec can be accomplished by setting the signal to the reset pin to low level for at least 50 s or setting the hw_rst bit in greg5 to 1. after a power -on reset or a hardware reset, the default register settings are used. t he codec will then enter the default state as described below: 1. all four channels are powered down; 2. all loopbacks and cutoff are disabled; 3. the dx1/du pin is selected for all channels to transmit pcm data. the dr1/dd pin is select ed for all channels to receive pcm data. 4. the master clock (mclk) frequency is 2.048 mhz; 5. in mpi mode, time slot 0 to time slot 3 are selected for channel 1 to channel 4 to transmit and receive data. the pcm data rate is the same as the bit clock (bclk) frequency. the pcm data is transmitted on the rising edges of bclk and received on the falling edges. in gci mode, time slot assignment is determined by the logic levels of the cclk/s0 and ci/s1 pins. the data rate is always 2.048 mhz, no matter 2.048 mhz or 4.096 mhz is applied to the dcl pin. the gci data is transfe rred via the du/dd pin on rising edges of dcl. 6. a-law is selected; 7. default register settings are selected; 8. all io pins are configured as inputs; 9. all maskable interrupts are ma sked by corresponding mask bits; 10.all function blocks including leve l meter, utd unit, fsk generator, tone generators etc., are disabled. 6.8.2 software reset each channel of the codec can be individually reset by a software reset command. the rch_sel[3:0] bits in greg5 determine whether channel 4 to channel 1 will be software reset or not. setting the sw_rst bit and any desired bit of rch_sel[3:0] to 1 will reset the corresponding channel. once a software reset is performed, the device will enter the following state: 1. the reset channel(s) are powered down; 2. all test loopbacks and cutoff on the reset channel(s) are disabled; 3. the dx1/du and dr1/dd pins are selected for the reset channel(s) to transmit and receive pcm data. 4. in mpi mode, time slot 0 to time slot 3 are selected for channel 1 to channel 4 to transmit and receive the pcm data. the pcm data rate is the same as the bit clock (bclk) frequency. the pcm data is transmitted on the rising edges of bclk and received on the falling edges. in gci mode, time slot assignment is determined by the logic levels of the cclk/s0 and ci/s1 pins. the data rate is always 2.048 mhz, no matter 2.048 mhz or 4.096 mhz is applied to the dcl pin. the gci data is trans ferred via du/dd pin on rising edges of dcl. 5. all default coefficients and regi ster setting except the highpass filter (the hpf bit in lreg5 is set to 1) are selected for the reset channel(s). 6. all io pins of the reset c hannel(s) are configured as inputs; 7. all maskable interrupts of the reset channel(s) are masked by corresponding mask bits. 94 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7 electrical characteristics 7.1 rslic electric al characteristics 7.1.1 rslic absolute maximum ratings ? note: stresses greater than those listed under absolu te maximum ratings may cause permanent da mage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 7.1.2 rslic recommended operating conditions ? 7.1.3 rslic thermal information ? 7.1.4 rslic power consumption ? ratings min. max. unit power supply voltage vdd ? 0.5 + 5v vdd-vbh 75 v tip/ring negative pulse vbh ? 0.7 v tip/ring positive pulse vdd + 0.7 v esd voltage (human body model) 1kv parameter min. max. unit operating temperature ? 40 + 85 c power supply voltage vdd +3.135 +3.465 v low battery power supply vbl ? 52 ? 20 v high battery power supply vbh ? 70 ? 52 v parameter min. max. unit thermal resistance 70 c/w maximum junction temperature (plastic) 150 c description min. typ. max. units test conditions rslic power consumption in power down mode 90 100 mw vdd = +3.3 v, vbh = ? 70 v, vbl = ? 48 v; without load.between the tip pin and the ring pin. rslic power consumption in standby mode 160 180 mw rslic power consumption in normal active mode 400 450 mw 95 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.2 codec electri cal characteristics 7.2.1 codec absolute maximum ratings ? note: stresses greater than those listed under absolu te maximum ratings may cause permanent da mage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 7.2.2 codec recommended operating conditions ? 7.2.3 codec digital interface ? 7.2.4 codec power dissipation ? ratings min. max. unit supply pins referred to the corresponding ground pin ? 0.3 4.6 v ground pins referred to any other ground pin ? 0.3 + 0.3 v supply pins referred to any other supply pin ? 0.3 + 0.3 v analog input and output pins ? 0.3 3.6 v digital input and output pins ? 0.3 5.5 v dc input and output current at any input or output pin (free from latch-up) 100 ma storage temperature ? 65 125 c ambient temperature under bias ? 40 85 c power dissipation 1w esd voltage (human body model) 2kv description min. typ. max. units test conditions supply pins referred to the corresponding ground pin +3.135 + 3.3 +3.465 v analog input pins referred to the ground pin 0+3.3v ambient temperature ? 40 + 85 c parameter description min. typ. max. units test conditions v il input low voltage 0.8 v all digital inputs v ih input high voltage 2.0 v all digital inputs v ol output low voltage 0.8 v i l = 4 ma v oh output high voltage vdd ? 0.6 v i l = ? 4 ma v aol output low voltage on relay driver pin 0.4 v i l = 10 ma v aoh output high voltage on relay driver pin vdd ? 0.6 v i l = ? 4 ma i i input current ? 10 10 a all digital inputs i oz output current in high-impedance digital pin ? 10 10 a c i input capacitance 5 pf parameter description min. typ. max. units test conditions vdd power supply voltage 3.3 v i dd1 operating current 95 ma i dd0 standby current 7 ma 96 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.3 chipset transmis sion characteristics 0 dbm0 of pcm bus is defined as 0.775 vrms for 600 ? load. 0 dbm0 of analog input or output of the codec is relative to the 0 dbm0 of the pcm bus output or input. unless otherwise noted, the analog input is a 0 dbm0, 1020 hz sine wave. the digital input is a pcm bit st ream equivalent to that obtained by passing a 0 dbm0, 1020 hz sine wave through an ideal enc oder. the output level is sin(x)/x-corrected. typical value s are tested at vdd = 3.3 v and t a = 25c. 7.3.1 absolute gain ? 7.3.2 gain tracking ? 7.3.3 frequency response ? 7.3.4 return loss ? parameter description min. typ. max. units test conditions g xa transmit gain, absolute ? 0.25 0.25 db signal output of 0 dbm0, normal mode g ra receive gain, absolute ? 0.25 0.25 db a-law or -law, pcm input of 0 dbm0, 1014 hz parameter description min. typ. max. units test conditions g tx transmit gain tracking + 3 dbm0 to ? 40 dbm0 ? 40 dbm0 to ? 50 dbm0 ? 50 dbm0 to ? 55 dbm0 ? 0.25 ? 0.5 ? 1.4 0.25 0.5 1.4 db tested by sinusoidal method, a-law or -law, f = 1014 hz, reference level ? 10 dbm0 g tr receive gain tracking + 3 dbm0 to ? 40 dbm0 ? 40 dbm0 to ? 50 dbm0 ? 50 dbm0 to ? 55 dbm0 ? 0.25 ? 0.5 ? 1.4 0.25 0.5 1.4 db tested by sinusoidal method, a-law or -law, f = 1014 hz, reference level ? 10 dbm0 parameter description min. typ. max. units test conditions g xr transmit gain, relative to g xa f = 50 hz f = 60 hz f = 300 hz to 3000 hz f = 3000 hz to 3400 hz f = 3600 hz f 4600 hz ? 0.25 ? 0.40 ? 30 ? 30 0.25 0.25 ? 0.10 ? 35 db the highpass filter is enabled. g rr receive gain, relative to g ra f < 300 hz f = 300 hz to 3000 hz f = 3000 hz to 3400 hz f = 3600 hz f 4600 hz ? 0.25 ? 0.40 0.10 0.25 0.25 ? 0.20 ? 35 db parameter description min. typ. max. units test conditions rl return loss (2-wire) 26 db 300 - 3400 hz hb hybrid balance (4-wire) 26 db 300 - 3400 hz l-4 input longitudinal interface loss 52 55 db 300 - 3400 hz l-t longitudinal conversion loss 52 55 db 300 - 3400 hz 97 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.3.5 group delay ? 7.3.6 distortion ? 7.3.7 noise ? parameter description min. typ. max. units test conditions d xr transmit delay, relative to 1800 hz f = 500 hz to 600 hz f = 600 hz to 1000 hz f = 1000 hz to 2600 hz f = 2600 hz to 2800 hz 80 80 50 280 s d rr receive delay, relative to 1800 hz f < 300 hz f = 300 hz to 3400 hz f = 3600 hz f 4600 hz 50 80 120 150 s dr round-trip delay 900 s parameter description min. ty p. max. units test conditions std x transmit signal to total distortion ratio ? 45 dbm0 ? 40 dbm0 ? 30 dbm0 ? 20 dbm0 ? 10 dbm0 3 dbm0 25 29 34 36 36 36 db output connection: l x = 0 dbr f = 1014 hz (c message weighted for -law, psophometrically weighted for a-law) std r receive signal to total distortion ratio ? 45 dbm0 ? 40 dbm0 ? 30 dbm0 ? 20 dbm0 ? 10 dbm0 3 dbm0 25 29 34 36 36 36 db input connection: l r = 0 dbr f = 1014 hz (c message weighted for -law, psophometrically weighted for a-law) parameter description min. ty p. max. units test conditions n xc transmit noise, c message weighted for -law 18 dbrnc0 n xp transmit noise, psophometrically weighted for a-law ? 68 dbm0p n rc receive noise, c message weighted for -law 12 dbrnc0 n rp receive noise, psophometrically weighted for a-law ? 78 dbm0 psr x power supply rejection, transmit f = 300 hz to 3.4 khz f = 3.4 khz to 20 khz 30 25 db vdd = 3.3 vdc+100 mvrms psr r power supply rejection, receive f = 300 hz to 3.4 khz f = 3.4 khz to 20 khz 30 25 db vdd = 3.3 vdc+100 mvrms, pcm code is positive lsb one 98 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.3.8 interchannel crosstalk ? parameter description min. ty p. max. units test conditions xt x-r transmit to receive crosstalk ? 85 ? 78 db 300 hz to 3400 hz, 0 dbm0 signal into vtac of interfering channel. idle pcm code into channel under test xt r-x receive to transmit crosstalk ? 85 ? 80 db 300 hz to 3400 hz, 0 dbm0 pcm code into inter- fering channel. vtac = 0 vrms for channel under test xt x-x transmit to transmit crosstalk ? 85 ? 78 db 300 hz to 3400 hz, 0 dbm0 signal into vtac of interfering channel. vtac = 0 vrms for channel under test xt r-r receive to receive crosstalk ? 85 ? 80 db 300 hz to 3400 hz, 0 dbm0 pcm code into inter- fering channel. idle pcm code into channel under test 99 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.4 codec timing characteristics 7.4.1 clock timing ? ? symbol description min. typ. max. units test conditions t1 cclk period 122 100 k ns t2 cclk pulse width 48 ns t3 cclk rise and fall time 25 ns t4 bclk period 122 ns t5 bclk pulse width 48 ns t6 bclk rise and fall time 15 ns t7 mclk pulse width 48 ns t8 mclk rise and fall time 15 ns t9 dcl period f = 2.048 khz f = 4.096 khz 488 244 ns t10 dcl rise and fall time 60 ns t11 dcl pulse width 90 ns ? figure - 43 clock timing t3 t3 cclk t1 t2 t2 t6 t6 bclk t4 t5 t5 t8 t8 mclk t7 t7 t10 t10 dcl t9 t11 100 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.4.2 microprocessor interface timing ? ? ? symbol description min. typ. max. units test conditions t12 cs setup time 15 ns t13 cs pulse width 8 ? n ? t1 (n 2) ns t14 cs off time 250 ns t15 input data setup time 30 ns t16 input data hold time 30 ns t17 slic output latch valid 1000 ns t18 output data turn on delay 50 ns t19 output data hold time 0 ns t20 output data turn off delay 50 ns t21 output data valid 0 50 ns ? figure - 44 mpi input timing ? figure - 45 mpi output timing t12 t15 t16 t14 t17 cclk cs ci rslic output t13 t12 t18 t19 t14 cclk cs co t13 t21 t20 101 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.4.3 pcm interface timing ? ? ? symbol description min. typ. max. units test conditions t22 bclk period 1) 122 ns t23 bclk high time 48 ns t24 fsc period 125 s t25 fsc setup time 25 t22 ? 50 ns t26 fsc hold time 50 ns t27 dr1/dr2 setup time 25 ns t28 dr1/dr2 hold time 5 ns t29 dx1/dx2 output delay 5 70 ns t30 dx1/dx2 output hold time 5 70 ns t31 dx1/dx2 output delay to high-z 5 70 ns t32 delay to tsx1 / tsx2 valid 2) 580ns t33 delay to tsx1 / tsx2 off 3) 580ns ? figure - 46 pcm interface timing (single clock mode) t25 t26 t22 t23 first bit t27 t28 first bit t29 t30 t31 bclk fsc dr1/dr2 dx1/dx2 t32 t33 t24 high z tsx1 / tsx2 102 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range notes: 1) the bclk frequency must be an integer multiple of the fsc frequency. the maximum bclk frequency is 8.192 mhz. the minimum bcl k frequency is 64 khz in compressed mode and 128 khz in linear mode if only one channel is used. the minimu m bclk frequency is 256 khz in compressed mode and 512 khz in linear mode if all four channels are used. 2) tsx1 or tsx2 typically delays from the fsc for 8 ? n ? t22 ns in compressed mode and 16 ? n ? t22 ns in linear mode, where n is the specified time slot (value of tt[6:0] in register lreg1). 3) t33 is defined to be the time when the tsx1 or tsx2 output achieves high level. 4) figure - 46 and figure - 47 show the timing of transmit at the rising edges of bclk and receive at the falling edges of it. ? figure - 47 pcm interface timing (double clock mode) t25 t26 t22 t23 t27 t28 first bit t29 t30 t31 bclk fsc dr1/dr2 dx1/dx2 t32 t33 t24 high z tsx1 / tsx2 first bit 103 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 7.4.4 gci interface timing ? ? symbol description min. typ. max. units test conditions t34 fsc rise and fall time 60 ns t35 fsc setup time 70 t9 ? 50 ns t36 fsc hold time 50 ns t37 fsc high pulse width 130 ns t38 du data delay time 100 ns t39 dd data delay time 110 ns t40 dd data hold time 50 ns ? figure - 48 gci interface timing du dd fsc dcl 4.096 mhz t35 t36 t37 t38 t38 t39 t40 t35 t37 b7 b7 du dd fsc dcl 2.048mhz t35 t36 t37 t38 t38 t39 t40 t35 t37 b7 b6 b7 b6 b7 b6 b0 detail a dcl fsc dd/du detail a 104 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 8 application circuits 8.1 application circuit for the internal ringing mode the rslic-codec chipset can provide an internal ringing signal wi thout any external components. the amplitude of the internal r inging signal can be up to 70 vp. the off-hook detection and ring tr ip detection are also internally performed. figure - 49 shows an application circuit for the internal ringing mode. figure - 49 application circuit for the internal ringing mode idt82v1671 vbh vbl vdd tis tip ring ris vcmb rsp rsn rt agnd bgnd cf m3 m2 m1 cs vcm dcp dcn vtdc vtac vl ca idt82v1074 (channel1) vddd vdda vddb rtin1 vl1 vtac1 vtdc1 acn1 dcn1 ca2_1 dcp1 gnda gndd fsc dcl/bclk int /int mclk reset co ci/s1 cclk/s0 cs mpi /gci acp1 ca1_1 io1_1 io2_1 io3_1 io4_1 cs1 m1 m2 m3 cnf vcm tsx1 dx1/du dr1/dd tsx2 dx2 dr2 rsync acn acp 14 16 13 15 9 10 11 12 8 21 20 19 18 52 15 17 56 55 54 47 48 49 50 36 37 38 39 ca1 ca2 40 41 33 34 32 31 +3.3vd +3.3va +3.3va 60 61 62 63 64 67 66 77 76 75 68 69 70 72 73 74 59 +3.3v vbl vbh 22 23 24 25 2 26 27 4 128 5 637 cf protection c int r s c stab c stab r prot r s r prot bgnd + + 0.1 f agnd 10 f 0.1 f 10 f cb 17 0.1 agnd agnd dgnd + 10 f 0.1 f dgnd agnd agnd 0.1 f 0.1 f agn d agnd bgnd cnf d1 (1 a/200 v) d2 (1 a/200 v) d3 (1 a/200 v) d4 1n4148 d5 1n4148 105 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 8.2 application circuit for the external ringing mode the chipset also supports the external ringing mode. figure - 50 shows an application circuit for the external ringing mode. figure - 50 application circui t for the external ringing mode table - 28 external componen ts in application circuits symbol value unit tolerance rating r prot 50 ? 5% 1 w r s 50 ? 1% 1 w r1, r2 100 k ? 10% r3, r6 150 ? 10% 1 w r4, r5, r7, r8 10 ? 10% c stab 22 nf 10% 100 v c int 0.47 f 10% 50 v ca1 0.047 f 10% ca2 0.047 f 10% cf 0.47 f 10% 50 v cnf 0.1 f 10% c1, c2 1 f 10% idt82v1671 vbh vbl vdd tis tip ring ris vcmb rsn rsp rt agnd bgnd cf m3 m2 m1 cs vcm dcp dcn vtdc vtac vl idt82v1074 (channel1) vddd vdda vddb rtin1 vl1 vtac1 vtdc1 acn1 dcn1 ca2_1 dcp1 gnda gndd fsc dcl/bclk int /int mclk reset co ci/s1 cclk/s0 cs mpi /gci acp1 ca1_1 io1_1 io2_1 io3_1 io4_1 cs1 m1 m2 m3 cnf vcm tsx1 dx1/du dr1/dd tsx2 dx2 dr2 rsync acn acp 16 13 15 9 10 11 12 8 21 20 19 18 52 15 17 56 55 54 47 48 49 50 36 37 38 39 ca1 ca2 40 41 33 34 32 31 22 24 23 25 2 26 27 4 637 cf protection r s c stab r prot r s r prot cnf +5v ring generator -48v dc 80vrms agnd bgnd c stab bgnd agnd dgnd agnd relay +3.3v vbl vbh 1 28 5 + + 0.1 f agnd 10 f 0.1 f 10 f ca 14 cb 17 agn d +3.3vd +3.3va +3.3va + 10 f 0.1 f dgnd agnd agnd 0.1 f 0.1 f 60 61 62 63 64 67 66 77 76 75 68 69 70 72 73 74 59 in4148 in4148 c1 c2 r1 r2 r3 r4 r5 r6 r7 r8 c int d4 d1 (1 a/200 v) d2 (1 a/200 v) d3 (1 a/200 v) 1n4148 d5 1n4148 d6 d7 106 rslic (idt82v1671) & codec (idt 82v1074) chipset industrial temperature range 9 ordering information rslic (idt82v1671): codec (idt82v1074): idt xxxxxxx x x dev ice ty pe blank process/ temperature range j 82v1671 industrial (-40 c to +85 c) plastic leaded chip carrier (plcc, pl28) ringing slic package idt xxxxxxx xx x dev ice ty pe blank process/ temperature range pf 82v1074 industrial (-40 c to +85 c) thin quad flat pack (tqfp, pk100) quad programmable pcm codec package 107 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for tech support: email: telecomhelp@idt.com phone: 408-330-1552 rslic (idt82v1671) & codec (idt82v1074) chipset indust rial temperature range data sheet document history 11/05/2002 pgs. 1, 17, 36, 44 - 48, 60, 63, 77 - 78, 83 - 85, 88, 94, 103, 104 01/09/2003 pgs. 1, 105 02/28/2003 pgs. 29, 66, 93, 103, 104 04/22/2003 pgs. 73, 93, 94 11/18/2003 pgs. 1, 19, 21, 29, 61, 63, 75 02/16/2004 pgs. 18, 19, 21, 26, 29, 60, 61, 63, 73, 75, 77, 83-85, 93, 94 |
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